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71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics general description the 71m6543ft/71m6543ht/71m6543gt/71m6543ght (71m654xt) are 4th-generation three-phase metering systems-on-chips (socs) with a 5mhz, 8051-compat - ible mpu core, low-power rtc with digital temperature compensation, flash memory, and lcd driver. our single converter technology ? with a 22-bit delta-sigma adc, seven analog inputs, digital temperature compensation, precision voltage reference, and a 32-bit computation engine (ce) support a wide range of metering applications with very few external components. the 71m654xt devices support optional interfaces to the maxim integrated 71m6x03 series of isolated sensors offering bom cost reduction, immunity to magnetic tam - per, and enhanced reliability. other features include an spi interface, advanced power management, ultra-low- power operation in active and battery modes, 5kb shared ram, and 64kb/128kb flash memory that can be pro - grammed in the field with code and/or data during meter operation and the ability to drive up to six lcd segments per seg driver pin. high processing and sampling rates combined with differential inputs offer a powerful platform for residential meters. a complete array of code development tools, demonstra - tion code, and reference designs enable rapid develop - ment and certification of meters that meet all ansi and iec electricity metering standards worldwide. the 71m654xt family operates over the industrial tem - perature range and comes in a 100-pin lead(pb)-free lqfp package. applications three-phase residential, commercial, and industrial energy meters beneits and features soc integration and unique isolation technique reduces bom cost without sacrificing performance ? 0.1% typical accuracy over 2000:1 current range ? exceeds iec 62053/ansi c12.20 standards ? four-quadrant metering ? 46-64hz line frequency range with the same calibration ? phase compensation (10o) ? independent 32-bit compute engine ? 64kb flash, 5kb ram (71m6543ft/71m6543ht) ? 128kb flash, 5kb ram (71m6543gt/71m6543ght) ? built-in flash security ? spi interface with flash program capability ? up to four pulse outputs with pulse count ? 8-bit mpu (80515), up to 5 mips ? full-speed mpu clock in brownout mode ? lcd driver allows up to 6 commons/up to 56 pins ? up to 51 multifunction dio pins ? hardware watchdog timer (wdt) ? two uarts for ir and amr ? ir led driver with modulation ? i 2 c/microwire? eeprom interface innovative isolation technology (requires companion 71m6xxx sensor, also from maxim integrated) eliminates current transformers ? four current sensor inputs with selectable differential mode ? selectable gain of 1 or 8 for one current input to support neutral current shunt ? high-speed wh/varh pulse outputs with programmable width digital temperature compensation improves system performance ? metrology compensation ? accurate rtc for tou functions with automatic temperature compensation for crystal in all power modes power management extends battery life during power outages ? three battery-backup modes - brownout mode (brn) - lcd mode (lcd) - sleep mode (slp) ? wake-up on pin events and wake-on timer ? 1a in sleep mode 19-6720; rev 7; 12/15 ordering information and typical operating circuit appear at end of data sheet. single converter technology is a registered trademark of maxim integrated products, inc. microwire is a registered trademark of national semiconductor corp. evaluation kit available downloaded from: http:///
maxim integrated 2 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 absolute maximum ratings ...................................................................... 7 electrical characteristics ........................................................................ 7 recommended external components ............................................................. 13 pin configuration ............................................................................. 14 pin descriptions .............................................................................. 15 block diagram ............................................................................... 19 hardware description .......................................................................... 20 analog front-end (afe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 signal input pins ................................................... ...................... 21 input multiplexer ................................................... ....................... 23 delay compensation .................................................. .................... 24 adc preamplifier ................................................... ...................... 25 analog-to-digital converter (adc) ................................................... ........ 25 fir filter ................................................... ............................ 25 voltage references ................................................... .................... 25 isolated sensor interface ................................................... ................ 25 digital computation engine (ce) ................................................... ............ 26 meter equations ................................................... ....................... 26 real-time monitor .................................................. ...................... 26 pulse generators ................................................... ...................... 26 xpulse and ypulse ................................................... .................. 27 vpulse and wpulse ................................................... ................. 27 80515 mpu core ................................................... ......................... 27 memory organization and addressing .................................................. ...... 27 program memory ................................................... ...................... 27 mpu external data memory (xram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 movx addressing ................................................... ..................... 27 dual data pointer ................................................... ...................... 28 internal data memory map and access ................................................... .... 28 special function registers ................................................... .............. 29 timers and counters ................................................... ................... 29 interrupts .................................................. ............................. 31 interrupt overview ................................................... ..................... 31 external mpu interrupts .................................................. ................. 31 on-chip resources .................................................. ....................... 31 downloaded from: http:///
maxim integrated 3 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table of contents ( continued) flash memory ................................................... ........................ 31 mpu/ce ram ................................................... ........................ 32 i/o ram ................................................... ............................. 32 crystal oscillator ................................................... ...................... 32 pll ................................................... ................................. 32 real-time clock (rtc) ................................................... ................. 33 rtc trimming ................................................... ........................ 33 rtc interrupts ................................................... ........................ 33 temperature sensor ................................................... ................... 33 battery monitor ................................................... ........................ 33 digital i/o and lcd segment drivers .................................................. ....... 34 lcd drivers ................................................... .......................... 34 square wave output ................................................... ................... 36 eeprom interface ................................................... .................... 36 two-pin eeprom interface .................................................. .............. 36 three-wire eeprom interface ................................................... ........... 36 uart .................................................. ................................ 36 spi slave port ................................................... ........................ 36 spi safe mode ................................................... ........................ 38 spi flash mode (sfm) ................................................... .................. 38 hardware watchdog timer ................................................... .............. 38 test ports ................................................... ............................ 38 functional description ......................................................................... 40 theory of operation ................................................... ...................... 40 battery modes ................................................... ........................... 40 brownout mode ................................................... ....................... 41 lcd only mode ................................................... ....................... 41 sleep mode .................................................. ........................... 42 applications information ........................................................................ 46 connecting 5v devices .................................................. .................... 46 direct connection of sensors ................................................... ............... 46 using the 71m6543ft/ht/gt/ght with local sensors ................................................... ....................... 46 using the 71m6543ft/ht/gt/ght with remote sensors ................................................... ..................... 46 metrology temperature compensation .................................................. ........ 46 connecting i 2 c eeproms ................................................... ................. 46 connecting three-wire eeproms .................................................. ........... 46 downloaded from: http:///
maxim integrated 4 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table of contents ( continued) uart0 ................................................... ................................. 46 optical interface ................................................... ......................... 46 reset ................................................... .................................. 47 mpu firmware library ................................................... .................... 47 meter calibration ................................................... ......................... 62 firmware interface ............................................................................ 62 overview: functional order .................................................. ................. 62 i/o ram map: details ................................................... ..................... 62 reading the info page ................................................... .................... 63 ce interface description ................................................... ................... 64 ce program ................................................... .......................... 64 ce data format ................................................... ....................... 64 constants ................................................... ............................ 64 environment ................................................... .......................... 64 ce calculations ................................................... ....................... 64 ce input data ................................................... ........................ 64 ce status and control ................................................... .................. 65 transfer variables ................................................... ..................... 65 ce flow diagrams ............................................................................ 65 pulse generation ................................................... ...................... 71 ce flow diagrams ............................................................................ 71 ordering information .......................................................................... 73 package information .......................................................................... 73 typical operating circuit ........................................................................ 74 revision history .............................................................................. 75 downloaded from: http:///
maxim integrated 5 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com list of figures figure 1. i/o equivalent circuits ................................................................. 18 figure 2. 71m6543ft/ht/gt/ght operating with local sensor s ....................................... 21 figure 3. 71m6543ft/ht/gt/ght operating with remote senso r for neutral current ....................... 22 figure 4. multiplexer sequence with neutral channel and rem ote sensors ............................... 23 figure 5. multiplexer sequence with neutral channel and cur rent transformers ........................... 24 figure 6. typical lcd waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7. optical interface (uart1) ............................................................... 37 figure 8. waveforms comparing voltage, current, energy per interval, and accumulated energy .............. 41 figure 9. typical voltage sense circuit using resistive divid er ......................................... 42 figure 10. typical current-sense circuit using current tran sformer in a single-ended configuration .......... 42 figure 11. typical current-sense circuit using current tran sformer in a differential configuration ............. 43 figure 12. typical current-sense circuit using shunt in a dif ferential configuration ........................ 43 figure 13. 71m6543ft/ht/gt/ght typical operating circuit u sing locally connected sensors .............. 44 figure 14. 71m6543ft/ht/gt/ght typical operating circuit u sing remote neutral current sensor ........... 45 figure 15. typical i 2 c operating circuit ........................................................... 47 figure 16. typical uart operating circuit ......................................................... 47 figure 17. typical reset circuits ................................................................. 47 figure 18. optical interface typical operating circuit ................................................. 47 figure 19. typical emulator connections .......................................................... 47 figure 20. ce data flow ? multiplexer and adc ..................................................... 71 figure 21. ce data flow ? offset, gain, and phase compensation ...................................... 72 figure 22. ce data flow ? squaring and summation ................................................. 72 downloaded from: http:///
maxim integrated 6 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com list of tables table 1. adc input configuration ................................................................ 25 table 2. inputs selected in multiplexer cycles ...................................................... 26 table 3. ckmpu clock frequencies .............................................................. 27 table 4. memory map ......................................................................... 28 table 5. internal data memory map .............................................................. 28 table 6. special function register map ........................................................... 29 table 7. timers/counters mode description ........................................................ 29 table 8. generic 80515 sfrs: location and reset values ............................................. 30 table 9. external mpu interrupts ................................................................. 31 table 10. flash banks ......................................................................... 32 table 11. test ports ........................................................................... 39 table 12. i/o ram locations in numerical order .................................................... 48 table 13. i/o ram locations in alphabetical order .................................................. 53 table 14. register and fuses for temperature sensing ............................................... 63 table 15. power equations ...................................................................... 65 table 16. ce raw data access locations ......................................................... 65 table 17. ce status register .................................................................... 66 table 18. ce configuration register .............................................................. 66 table 19. sag threshold and gain adjustment registers .............................................. 67 table 20. ce transfer registers ................................................................. 67 table 21. ce pulse generation parameters ........................................................ 68 table 22. other ce parameters .................................................................. 69 table 23. ce calibration parameters ............................................................. 70 downloaded from: http:///
maxim integrated 7 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com electrical characteristics (all voltages referenced to gnda.) supplies and ground pins v v3p3sys , v v3p3a ............................................... -0.5v to +4.6v v bat , v bat_rtc ................................................... -0.5v to +4.6v gndd ................................................................... -0.1v to +0.1v analog output pins v ref ....................... -10ma to +10ma, -0.5v to (v v3p3a + 0.5v) v dd .......................................... -10ma to +10ma, -0.5v to +3.0v v v3p3d .................................... -10ma to +10ma, -0.5v to +4.6v v lcd ........................................ -10ma to +10ma, -0.5v to +6.0v analog input pins iadc0-7, vadc8-10 ........................... -10ma to +10ma, -0.5v to (v v3p3a + 0.5v) xin, xout ............................... -10ma to +10ma, -0.5v to +3.0v seg and segdio pins configured as seg or com drivers . -1ma to +1ma, -0.5v to +6.0v configured as digital inputs .... -10ma to +10ma, -0.5v to +6.0v configured as digital outputs ............ -10ma to +10ma, -0.5v to (v v3p3d + 0.5v) digital pins inputs (pb, reset, rx, ice_e, test) ........... -10ma to +10ma, -0.5v to +6.0v outputs (tx) .......... -10ma to +10ma, -0.5v to (v v3p3d + 0.5v) temperature operating junction temperature (peak, 100ms) ............. +140c operating junction temperature (continuous) ................ +125c storage temperature ........................................ -45c to +140c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings (limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaran - teed by design and characterization.) parameter conditions min typ max units recommended operating conditions v v3p3sys and v v3p3a supply voltage precision metering operation 3.0 3.6 v v bat pll_fast = 1 2.65 3.8 v pll_fast = 0 2.40 3.8 v bat_rtc 2.0 3.8 v operating temperature -40 +85 c input logic levels digital high-level input voltage (v ih ) 2 v digital low-level input voltage (v il ) 0.8 v input pullup current, (i il ) e_ rtxt, e_rst, e_tclk 10 100 a input pullup current, (i il ) opt_ rx, opt_tx 10 100 a input pullup current, (i il ) spi_ csz (segdio36) 10 100 a input pullup current, (i il ) other digital inputs -1 +1 a input pulldown current (i ih ), ice_e, reset, test 10 100 a input pulldown current, (i ih ) other digital inputs -1 +1 a downloaded from: http:///
maxim integrated 8 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com electrical characteristics (continued) (limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaran - teed by design and characterization.) parameter conditions min typ max units output logic levelsdigital high-level output voltage (v oh ) i load = 1ma v v3p3d - 0.4 v i load = 15ma (note 1) v v3p3d - 0.8 v digital low-level output voltage (v ol ) i load = 1ma 0 0.4 v i load = 15ma (note 1) 0 0.8 v battery monitor battery voltage equation: 3.3 + (bsense - bnom3p3) x 0.0252 + stemp x 2.79e-5 v measurement error v bat = 2.0v -3.5 +3.5 % v bat = 2.5v -3.5 +3.5 v bat = 3.0v -3.0 +3.0 v bat = 3.8v -3.0 +3.0 input impedance 260 k? passivation current i bat (bcurr = 1) - i bat (bcurr = 0) 50 100 165 a temperature monitor temperature measurement equation 22.15 + stemp x 0.085 - 0.0023 x stemp x [(stemp t85p -stemp t22p ) /(t 85p - t 22p ) - 12.857] c temperature error (note 1) t a = +85c -3.2 +3.2 c t a = 0c to +70c -2.65 +2.65 t a = -20c -3.4 +3.4 t a = -40c -3.8 +3.8 v bat_rtc charge per measurement 2 c duration of temperature measurement after temp_ start 22 40 ms supply current v v3p3a + v v3p3sys supply current (note 1) v v3p3a = v v3p3sys = 3.3v; mpu_div = 3 (614khz mpu clock); pll_fast = 1; pre_e = 0 7.2 8.5 ma pll_fast = 0 2.9 3.8 pre_e = 1 7.3 8.7 pll_fast = 0, pre_e = 1 3.0 3.9 dynamic current 0.4 0.6 ma/mhz downloaded from: http:///
maxim integrated 9 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com electrical characteristics (continued) (limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaran - teed by design and characterization.) parameter conditions min typ max units v bat current mission mode -300 +300 na brownout mode 2.4 3.2 ma lcd mode (external v lcd ) 0.4 108 na lcd mode (internal v lcd from dac) 3.0 16 a lcd mode (v bat ) 1.4 3.8 a sleep mode -300 +300 na v bat_rtc current brownout mode 400 650 na lcd mode 1.8 4.1 a sleep mode, t a 25c 0.7 1.7 a sleep mode, t a = 85c (note 1) 1.5 3.2 a flash write current maximum lash write rate 7.1 9.3 ma v v3p3d switch on-resistance v v3p3sys to v v3p3d , i v3p3d 1ma 11 ? v bat to v v3p3d , i v3p3d 1ma 11 i oh 9 ma internal power fault comparator response time 100mv overdrive, falling 20 200 s 100mv overdrive, rising 200 falling threshold, 3.0v comparator 2.83 2.93 3.03 v falling threshold, 2.8v comparator 2.71 2.81 2.91 v difference between 3.0v and 2.8v comparators 47 136 220 mv falling threshold, 2.25v comparator 2.14 2.33 2.51 v falling threshold, 2.0v comparator 1.90 2.07 2.23 v difference between 2.25v and 2.0v comparators 0.15 0.25 0.365 v hysteresis t a = +22c 3.0v comparator 13 45 81 mv 2.8v comparator 17 42 79 2.25v comparator 7 33 71 2.0v comparator 4 28 83 downloaded from: http:///
maxim integrated 10 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com electrical characteristics (continued) (limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaran - teed by design and characterization.) parameter conditions min typ max units 2.5v regulator v v2p5 output voltage v v3p3 = 3.0v to 3.8v, i load = 0ma 2.55 2.65 2.75 v v v2p5 load regulation v bat = 3.3v, v v3p3 = 0v, i load = 0ma to 1ma 40 mv dropout voltage i load = 5ma 440 mv i load = 0ma 200 pssr i load = 0ma 5 mv/v crystal oscillator maximum output power to crystal 1 w pll pll settling time power-up 3 ms pll_fast transition, low to high 3 pll_fast transition, high to low 3 mode transition, sleep to mission 3 lcdv lcd current v lcd = 3.3v, lcd frequency = 512hz, all segments on 8.1 a v lcd = 3.3v, lcd frequency = 256hz, all segments on 4.6 v lcd = 3.3v, all segments off 2.1 v lcd = 5.0v, lcd frequency = 512hz, all segments on 12.0 v lcd = 5.0v, lcd frequency = 256hz, all segments on 4.6 v lcd = 5.0v, all segments off 3.0 v ref v ref output voltage t a = +22c 1.193 1.195 1.197 v v ref output impedance i load = -10a to +10a 3.2 k? v ref power supply sensitivity v v3p3a = 3.0v to 3.6v -1.5 +1.5 mv/v v ref temperature sensitivity (note 1) v reft = v ref22 + (t-22)tc 1 + (t-22) 2 tc 2 v 71m6543ft/71m6543gt tc 1 = 151 - 2.77 x trimt v/c 71m6543ht/71m6543ght tc 1 = 33.264 + 0.08 x trimt + 1.587 x (trimbgb - trimbgd) v/c tc 2 = -0.528 - 0.00128 x trimt v/c 2 v ref error (note 1) 71m6543ft/71m6543gt (-40c to +85c) -40 +40 ppm/c 71m6543ht/71m6543ght (-40c to -20c) -16 +16 71m6543ht/71m6543ght (-20c to +85c) -10 +10 downloaded from: http:///
maxim integrated 11 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com electrical characteristics (continued) (limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaran - teed by design and characterization.) parameter conditions min typ max units adc recommended input range (all analog inputs, relative to v v3p3a ) -250 +250 mv peak recommended input range, iadc0-iadc1, preamp enabled -31.25 +31.25 mv peak input impedance f in = 65hz 40 100 k? adc gain error vs. power supply v in = 200mv peak, 65hz, v v3p3a = 3.0v to 3.6v -30 +70 ppm/% input offset voltage differential or single-ended modes -10 +10 mv thd 250mv peak, 65hz, 64k points, blackman-harris window, fir_len = 2, adc_div = 1, pll_fast = 1, mux_div = 2 -93 db 20mv peak, 65hz, 64k points, blackman-harris window, fir_len = 2, adc_div = 1, pll_fast = 1, mux_div = 2 -90 lsb size fir_len = 2, adc_div = 1, pll_fast = 1, mux_ div = 2 151 nv digital full scale fir_len = 2, adc_div = 1, pll_fast = 1, mux_ div = 2 2,097,152 lsb preamplifier differential gain 7.88 7.98 8.08 v/v gain variation vs. temperature t a = -40c to +85c (note 1) -30 -10 +15 ppm/c gain variation vs. v3p3 v v3p3 = 2.97v to 3.63v (note 1) -100 +100 ppm/% phase shift (note 1) +10 +22 m preamp input current 3 6 9 a thd, preamp + adc v in = 30mv -88 db v in = 15mv -88 preamp input offset voltage iadc0 = iadc1 = v v3p3 + 30mv -0.63 mv iadc0 = iadc1 = v v3p3 + 15mv -0.57 iadc0 = iadc1 = v v3p3 -0.56 iadc0 = iadc1 = v v3p3 - 15mv -0.56 iadc0 = iadc1 = v v3p3 - 30mv -0.55 phase shift over temperature (note 1) -0.03 +0.03 m /c downloaded from: http:///
maxim integrated 12 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com electrical characteristics (continued) (limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaran - teed by design and characterization.) parameter conditions min typ max units flash memory endurance 20,000 cycles data retention t a = +25c 100 years byte writes between erase operations 2 cycles write time, per byte per 2 bytes if using spi 50 s page erase time 22 ms mass erase time 22 ms spi data-to-clock setup time 10 ns data hold time from clock 10 ns output delay, clock to data 40 ns cs-to-clock setup time 10 ns hold time, cs to clock 15 ns clock high period 40 ns clock low period 40 ns clock frequency (as a multiple of cpu frequency) 2.0 mhz/mhz space between spi transactions 4.5 cpu cycles eeprom interface i 2 c scl frequency mpu clock = 4.9mhz, using interrupts 310 khz mpu clock = 4.9mhz, bit-banging dio2-dio3 100 3-wire write clock frequency mpu clock = 4.9mhz, pll_fast = 0 160 khz mpu clock = 4.9mhz, pll_fast = 1 490 reset reset pulse width (note 1) 5 s reset pulse fall time (note 1) 1 s internal calendar year date range 2000 2255 years downloaded from: http:///
maxim integrated 13 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com recommended external components note 1: parameter not tested in production, guaranteed by design to six-sigma. note 2: if the capacitor values of cxs = 15pf and cxl = 10pf have already been installed, then changing the cxl value to 33pf and leaving cxs = 15pf would minimize rework. name from to function value units c1 v v3p3a gnda bypass capacitor for 3.3v supply 0.1 20% f c2 v v3p3d gndd bypass capacitor for 3.3v output 0.1 20% f csys v v3p3sys gndd bypass capacitor for v v3p3sys 1.0 30% f cvdd v dd gndd bypass capacitor for v dd 0.1 20% f cvlcd v lcd gndd bypass capacitor for v lcd pin 0.1 20% f xtal xin xout 32.768 khz crystal; electrically similar to ecs .327-12.5-17x, vishay xt26t or suntsu scp6C 32.768khz tr (load capacitance 12.5pf) 32.768 khz cxs (note 2) xin gnda load capacitor values for crystal depend on crystal speciications and board parasitics. nominal values are based on 3pf allowance for the sum of board and chip capacitances. 22 10% pf cxl (note 2) xout gnda 22 10% pf downloaded from: http:///
maxim integrated 14 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com pin coniguration 1 75 2 74 3 73 4 72 5 71 7 69 8 68 9 67 25 51 top view 6 70 11 65 12 64 13 63 15 61 16 60 17 59 10 66 14 62 18 58 19 57 20 56 22 54 23 53 24 52 21 55 lqfp (14mm x 14mm) 26 100 27 99 28 98 29 97 30 96 31 95 32 94 33 93 34 92 35 91 36 90 37 89 38 88 39 87 40 86 41 85 42 84 43 83 44 82 45 81 46 80 47 79 48 78 49 77 50 76 + 71m6543 ft 71m6543ht 71m6543gt 71m6543ght spi_di/segdio38 spi_csz/segdio36 com1com2 com3 com0 segdio27/com4 spi_do/segdio37 segdio26/com5 segdio25segdio24 segdio23 segdio22 segdio21 segdio20 segdio19 segdio35segdio33 segdio32 segdio30 segdio29 segdio31segdio28 segdio34segdio18 segdio17 segdio1/vpulse segdio3/sdata n.c. opt_rx/segdio5 5 segdio16segdio15 segdio14 segdio13 segdio10 segdio11 segdio12 segdio9 segdio8/di segdio7/ypulsesegdio6/xpulse segdio5segdio4 segdio2/sdck segdio0/wpulse segdio54 n.c.n.c. n.c. n.c. tx v v3p3d v v3p3sys xingndd v bat ice_esegdio52 opt_tx/segdio51 iadc3 iadc2 gndav bat_rtc e_rxtx/seg48e_tclk/seg49 e_rst/seg50 rx segdio53 v dd n.c. n.c.iadc4 iadc5 iadc6 iadc7 tmuxout/seg47 segdio45 vadc10 v v3p3a gnda vadc8 pbv lcd testxout iadc0iadc1 reset tmux2out/seg46 segdio44 segdio43 segdio42 segdio41 segdio40 spi_cki/segdio39v ref n.c.n.c. n.c. vadc9 downloaded from: http:///
maxim integrated 15 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com pin descriptions pin name type circuit function 100 power and ground pins 72, 80 gnda p analog ground. this pin should be connected directly to the ground plane. 62 gndd p digital ground. this pin should be connected directly to the ground plane. 85 v v3p3a p analog power supply. a 3.3v power supply should be connected to this pin. v v3p3a must be the same voltage as v v3p3sys . 69 v v3p3sys p system 3.3v supply. this pin should be connected to a 3.3v power supply. 61 v v3p3d o 13 auxiliary voltage output of the chip. in mission mode, this pin is connected to v v3p3sys by the internal selection switch. in brn mode, it is internally connected to v bat . v v3p3d is loating in lcd and sleep mode. a 0.1f bypass capacitor to ground must be connected to this pin. 60 v dd o output of the 2.5v regulator. this pin is powered in msn and brn modes. a 0.1f bypass capacitor to ground should be connected to this pin. 89 v lcd o output of the lcd dac. a 0.1f bypass capacitor to ground should be connected to this pin. 70 v bat p 12 battery backup pin to support the battery modes (brn, lcd). a battery or super capacitor is to be connected between v bat and gndd. if no battery is used, connect v bat to v v3p3sys. 71 v bat_rtc p 12 rtc and oscillator power supply. a battery or super capacitor is to be connected between v bat and gndd. if no battery is used, connect v bat_ rtc to v v3p3sys . analog pins 87, 86 iadc0iadc1 i 6 differential or single-ended line current sense inputs. these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of current sensors. unused pins must be tied to v v3p3a . pins iadc2-iadc3, iadc4-iadc5 and iadc6-iadc7 may be conigured for communication with the remote sensor interface (71m6x03). 68, 67 iadc2iadc3 66, 65 iadc4iadc5 64, 63 iadc6iadc7 84, 83, 82 vadc8 (va), vadc9 (vb), vadc10 (vc) i 6 line voltage sense inputs. these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of resistor- dividers. unused pins must be tied to v v3p3a . 88 v ref o 9 voltage reference for the adc. this pin should be left unconnected (loating). 75 xin i 8 crystal inputs. a 32.768khz crystal should be connected across these pins. typically, a 22pf capacitor is also connected from xin to gnda and a 22pf capacitor is connected from xout to gnda. it is important to minimize the capacitance between these pins. see the crystal manufacturer data sheet for details. if an external clock is used, a 150mv p-p clock signal should be applied to xin, and xout should be left unconnected. 76 xout o downloaded from: http:///
maxim integrated 16 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com pin descriptions (continued) pin name type circuit function 100 digital pins 12C15 com0Ccom3 o 5 lcd common outputs. these four pins provide the select signals for the lcd display. 45 segdio0/wpulse i/o 3, 4, 5 multiple-use pins. conigurable as either lcd segment driver or dio. alternative functions with proper selection of associated i/o ram registers are: segdio0 = wpulse segdio1 = vpulse segdio2 = sdck segdio3 = sdata segdio6 = xpulse segdio7 = ypulse segdio8 = di segdio16 = rx3 segdio17 = tx3 unused pins must be conigured as outputs or terminated to v3p3/gndd. 44 segdio1/vpulse 43 segdio2/sdck 42 segdio3/sdata 41 segdio4 39 segdio5 38 segdio6/xpulse 37 segdio7/ypulse 36 segdio8/di 35C30 segdio[9:14] 29C27 segdio[15:17] 25 segdio[18] 24C18 segdio[19:25] 11C4 segdio[28:35] 95C94 segdio[44:45] 99C96 segdio[40:43] 52 segdio52 51 segdio53 47 segdio54 17 segdio26/com5 i/o 3, 4, 5 multiple-use pins. conigurable as either lcd segment driver or dio with alternative function (lcd common drivers). 16 segdio27/com4 3 spi_csz/segdio36 i/o 3, 4, 5 multiple-use pins. conigurable as either lcd segment driver or dio with alternative function (spi interface). 2 spi_do/segdio37 1 spi_di/segdio38 100 spi_cki/segdio39 53 opt_tx/segdio51 i/o 3, 4, 5 multiple-use pins, conigurable as either lcd segment driver or dio with alternative function (optical port/uart1) 46 opt_rx/segdio55 58 e_rxtx/seg48 i/o 1, 4, 5 multiuse pins. conigurable as either emulator port pins (when ice_e pulled high) or lcd segment drivers (when ice_e tied to gnd). 56 e_rst/seg50 57 e_tclk/seg49 o 4, 5 59 ice_e i 2 ice enable. when zero, e_rst, e_tclk, and e_rxtx become seg50, seg49, and seg48, respectively. for production units, this pin should be pulled to gnd to disable the emulator port. 92 tmuxout/seg47 o 4, 5 multiple-use pins. conigurable as either multiplexer/clock output or lcd segment driver using the i/o ram registers. 93 tmux2out/seg46 91 reset i 2 chip reset. this input pin is used to reset the chip into a known state. for normal operation, this pin is pulled low. to reset the chip, this pin should be pulled high. this pin has an internal 30fa (nominal) current source pulldown. no external reset circuitry is necessary. downloaded from: http:///
maxim integrated 17 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com pin descriptions (continued) i = input, o = output, p = power pin name type circuit function 100 55 rx i 3 uart0 input. if this pin is unused it must be terminated to v v3p3d or gndd. 54 tx o 4 uart0 output 81 test i 7 enables production test. this pin must be grounded in normal operation. 90 pb i 3 pushbutton input. this pin must be at gndd when not active or unused. a rising edge sets the wf_pb lag. it also causes the part to wake up if it is in slp or lcd mode. pb does not have an internal pullup or pulldown resistor. 26, 40, 48, 49, 50, 73, 74, 77, 78, 79, 84 n.c. n.c. no connection. do not connect these pins. downloaded from: http:///
maxim integrated 18 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 1. i/o equivalent circuits digital input equi va lent circuit type 1: standard digi ta l inpu t or pin configured as dio input with internal pull-up lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg v3p3d v3p3d 110k cmosinput digital input pin digital input type 2: pin configured as dio input with internal pull-up v3p3d 110k cmosinput digital input pin lcd segoutput pin lcd driver gndd gndd gndd analog input equivalent circuit type 6: adc input vref equivalent circuit type 9: vref v3p3d vrefpin from internal reference gnda v2p5 equivalent circuit type 10: v2p5 v3p3d v2p5pin from internal reference gndd v3p3d tomux analog input pin gnda digital input type 3: standard digi ta l inpu t or pin configured as dio input v3p3d cmosinput digital input pin gndd digital output equi va lent circuit type 4: standard digi ta l output or pin configured as dio output v3p3d v3p3d cmos output digital output pin gndd compara to r input equi va lent circuit type 7: compara to r input vlcd equivalent circuit type 11 : vlcd power v3p3d to compara to r compara to r input pin gnda lcddrivers vlcd pin gndd oscilla to r equi va lent circuit type 8: oscilla to r i/o v3p3d equivalent circuit type 13: v3p3d tooscilla to r oscilla to r pin gndd vbat equivalent circuit type 12: vba t power powerdown circuits vbat pin gndd 10 40 v3p3dpin from v3p3sys from vbat downloaded from: http:///
maxim integrated 19 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com block diagram iadc0 mux and preamp xin xout vref ckadc ce mpu (80515) opt_rx/ segdio55 opt_tx/ segdio51/ wpulse/ va rpulse reset vbias emulator po rt 3 ce_busy optical interface uart0 tx rx xfer busy 6 com[0:5] vlc2 lcd driver cedata 0x000...0x2ff 0x0000...0x13ff prog 0x000...0x3ff data 0x0000...0xffff program 0x0000...0xffff 0x0000... 0xffff digital i/o 0x2000...0x20ff i/o ram memory share memory share 16 8 rtclk rtclk (32khz) mux_sync ckmpu 4.9mhz ckce 4.9mhz ck3232khz 4.9mhz 4.9mhz 8 8 8 power fault detection gndd v3p3dvbat voltage regul at or 2.5v to logic vdd mpu_rstz faultz wake configuration pa rameters gnda v3p3a vbias cross clock gen oscillator 32khz ck32 mck pll vref div adc mux ctrl strt mux mux ckfir rtm segdio pins wpulsevarpulse wpulse varpulse test testmode vlc1 vlc0 ckmpu_2x ckmpu_2x sdck sdout sdin e_rxtx/seg48 e_tclk/seg49 e_rst/seg50 flash 64/128kb v3p3a eeprom interface ck_4x lcd_gen pb rtc vbias 16 e_rxtxe_tclk e_rst ice_e ? ad converter vref v3p3sys test mux vlcd vlcd vo lt age boos t mpu ram 5kb 22 spi vstat vbat_rtc iadc1iadc2 iadc3 va dc9 (vb) va dc10 (vc) seg pins 2 test mux 2 non-volatile configuration ram configuration ram (i/o ram) bat test temp sensor rtm fir 32 ce control 32-bit compute engine iadc4 iadc5iadc6 iadc7 va dc8 (va) downloaded from: http:///
maxim integrated 20 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com hardware description the 71m6543ft/ht/gt/ght single-chip energy meter ics integrate all primary functional blocks required to implement a solid-state residential electricity meter. included on the chip are the following: ? an analog front-end (afe) featuring a 22-bit second- order sigma-delta adc ? an independent 32-bit digital computation engine (ce) to implement dsp functions ? an 8051-compatible microprocessor (mpu) which executes one instruction per clock cycle (80515) ? a precision voltage reference (v ref ) ? a temperature sensor for digital temperature compensation: ? metrology digital temperature compensation (mpu) ? automatic rtc digital temperature compensation operational in all power states ? lcd drivers ? ram and flash memory ? a real-time clock (rtc) ? a variety of i/o pins ? a power-failure interrupt ? a zero-crossing interrupt ? selectable current sensor interfaces for locally-connect - ed sensors as well as isolated sensors (i.e., using the 71m6x03 companion ic with a shunt resistor sensor) ? resistive shunt and current transformers are supported resistive shunts and current transformer (ct) current sensors are supported. resistive shunt current sensors may be connected directly to the 71m654xt device or isolated using a companion 71m6x03 isolator ic in order to implement a variety of metering configurations. an inexpensive, small pulse transformer is used to isolate the 71m6x03 isolated sensor from the 71m654xt. the 71m654xt performs digital communications bidirectionally with the 71m6x03 and also provides power to the 71m6x03 through the isolating pulse transformer. isolated (remote) shunt current sensors are connected to the differential input of the 71m6x03. included on the 71m6x03 companion isolator chip are: ? digital isolation communications interface ? an analog front-end (afe) ? a precision voltage reference (v ref ) ? a temperature sensor (for digital temperature compen - sation) ? a fully differential shunt resistor sensor input ? a preamplifier to optimize shunt current sensor perfor - mance ? isolated power circuitry obtains dc power from pulses sent by the 71m654xt in a typical application, the 32-bit compute engine (ce) of the 71m654xt sequentially processes the samples from the voltage inputs on analog input pins and from the external 71m6x03 isolated sensors and performs calculations to measure active energy (wh) and reactive energy (varh), as well as a 2 h, and v 2 h for four-quadrant metering. these measurements are then accessed by the mpu, processed further and output using the peripheral devices available to the mpu. in addition to advanced measurement functions, the clock function allows the 71m6543ft/ht/gt/ght to record time-of-use (tou) metering information for multi-rate applications and to time-stamp tamper or other events. measurements can be displayed on 3.3v lcds commonly used in low-temperature environments. flexible mapping of lcd display segments facilitate integration of existing custom lcds. design trade-off between the number of lcd segments and dio pins can be implemented in software to accommodate various requirements. in addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement and rtc accuracy, e.g., to meet the requirements of ansi and iec standards. temperature-dependent external components such as crystal oscillator, resistive shunts, current transformers (cts) and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range. one of the two internal uarts is adapted to support an infrared led with internal drive and sense configuration and can also function as a standard uart. the optical output can be modulated at 38khz. this flexibility makes it possible to implement amr meters with an ir interface. a block diagram of the ic is shown in figure 1 . downloaded from: http:///
maxim integrated 21 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com analog front-end (afe) the afe functions as a data acquisition system, controlled by the mpu. when used with locally connected sensors, as shown in figure 2 , the analog input signals (iadc0-iadc7, vadc8-vadc10) are multiplexed to the adc input and sampled by the adc. the adc output is decimated by the fir filter and stored in ce ram where it can be accessed and processed by the ce. when remote isolated sensors are connected to the 71m6543ft/ht/gt/ght using 71m6x03 remote sensor interfaces, the input multiplexer is bypassed. instead, the extracted modulator bit stream is passed directly to a dedicated decimation filter. the output of the decimation filter is then directly stored in the appropriate ce ram location without making use of a multiplexer cycle. signal input pins the 71m6543ft/ht/gt/ght features eleven adc inputs. iadc0-iadc7 are intended for use as current sensor inputs. these eight current sensor inputs can be config - ured as four single-ended inputs, or (more frequently) can be paired to form four differential inputs. for best perfor - mance, it is recommended to configure the current sen - sor inputs as differential inputs. the first differential input (iadc0-iadc1) features a preamplifier with a selectable gain of 1 or 8, and is intended for direct connection to a shunt resistor sensor, and can also be used with a current transformer (ct). the remaining differential pairs may be figure 2. 71m6543ft/ht/gt/ght operating with local sensors ? adc converter vref mux vref vref va dc 22 fir iadc6 iadc0 va dc10 (va) iadc1 iadc7 71m6543ft/ht/gt/ght ce ram *in = optional neutral current in* ct va dc10 (vb) va dc10 (vc) i a iadc2iadc3 i b iadc4iadc5 i c downloaded from: http:///
maxim integrated 22 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 3. 71m6543ft/ht/gt/ght operating with remote sensor for neutral current used with cts, or may be enabled to interface to a remote 71m6x03 isolated current sensor providing isolation for a shunt resistor sensor using a low cost pulse transformer. the remaining inputs (vadc8-vadc10) are single-ended and sense line voltage. these single-ended inputs are referenced to the v v3p3a pin. all analog signal input pins measure voltage. in the case of shunt current sensors, currents are sensed as a voltage drop in the shunt resistor sensor. referring to figure 2 , shunt sensors can be connected directly to the 71m654xt (referred to as a local shunt sensor) or connected via an isolated 71m6x03 (referred to as a remote shunt sensor) ( figure 3 ). in the case of current transformers, the current is measured as a voltage across a burden resistor that is connected to the secondary winding of the ct. meanwhile, line voltages are sensed through resistive voltage dividers. pins iadc0-iadc1 can be programmed individually to be differential or single-ended. for most applications iadc0- iadc1 are configured as a differential input to work with a shunt or ct directly interfaced to the iadc0-iadc1 differential input with the appropriate external signal con - ditioning components. ? adc converter vref mux vref vref va dc 22 22 fir iadc0 va dc8 (va) iadc1 ce ram local shunt in* va dc9 (vb) va dc10 (vc) remote shunt ic 71m6543ft/ht/gt/ght 71m6x03 * in = optional neutral current iadc6iadc7 spsn inp inn digital isolation interface 22 remote shunt ib 71m6x03 iadc4iadc5 spsn inp inn digital isolation interface 22 remote shunt ia 71m6x03 iadc2iadc3 spsn inp inn digital isolation interface downloaded from: http:///
maxim integrated 23 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com the performance of the iadc0-iadc1 pins can be enhanced by enabling a preamplifier with a fixed gain of 8. when the pre_e bit = 1, iadc0-iadc1 become the inputs to the 8x preamplifier, and the output of this amplifier is supplied to the multiplexer. the 8x amplification is useful when current sensors with low sensitivity, such as shunt resistors, are used. with pre_e set, the iadc0-iadc1 input signal amplitude is restricted to 31.25 mv peak. when shunt resistors are used as current sense ele - ments on all current inputs, the iadc0-iadc1 pins are configured for differential mode to interface to a local shunt by setting the diffa_e control bit. meanwhile, the iadc2-iadc7 pins are re-configured as digital balanced pair to communicate with a 71m6x03 isolated sensor interface by setting the rmt_e control bit. the 71m6x03 communicates with the 71m654xt using a bidirectional digital data stream through an isolating low-cost pulse transformer. the 71m654xt also supplies power to the 71m6x03 through the isolating transformer. when using current transformers the iadc2-iadc7 pins are configured as local analog inputs (rmt_e = 0). the iadc0-iadc1 pins cannot be configured as a remote sensor interface. input multiplexer when operating with local sensors, the input multiplexer sequentially applies the input signals from the analog input pins to the input of the adc. one complete sampling sequence is called a multiplexer frame. the multiplexer of the 71m6543ft/ht/gt/ght can select up to seven input signals (three voltage inputs and four current inputs) per multiplexer frame. the multiplexer always starts at state 1 and proceeds until as many states as determined by mux_div[3:0] have been converted. the 71m6543ft/ht/gt/ght requires ce code that is writ - ten for the specific application. moreover, each ce code requires specific afe and mux settings in order to function properly. contact maxim integrated for specific information about alternative ce codes. for a polyphase configuration with neutral current sens - ing using shunt resistor current sensors and the 71m6xx3 isolated sensors, as shown in figure 3 , the iadc0-iadc1 input must be configured as a differential input, to be con - nected to a local shunt. the local shunt connected to the iadc0-iadc1 input is used to sense the neutral current. the voltage sensors (vadc8-vadc10) are also directly connected to the 71m6543ft/ht/gt/ght and are also routed though the multiplexer. meanwhile, the iadc2- iadc7 current inputs are configured as remote sensor digital interfaces and the corresponding samples are not routed through the multiplexer. for a polyphase configuration with optional neutral current sensing using current transformer (cts) sensors, all four current sensor inputs must be configured as differential inputs. iadc2-iadc3 is connected to phase a, iadc4- iadc5 is connected to phase b, and iadc6-iadc7 is connected to phase c. the iadc0-iadc1 current sensor input is optionally used to sense the neutral current for anti-tampering purposes. the voltage sensors (vadc8-vadc10), typically resistive dividers, are directly connected to the 71m6543ft/ht/gt/ght. no 71m6xx3 isolated sensors are used in this configuration and all signals are routed though the multiplexer. the multiplexer sequence shown in figure 4 corresponds to the configuration shown in figure 3 . the frame duration is 13 ck32 cycles (where ck32 = 32,768hz), therefore, the resulting sample rate is 32,768 hz/13 = 2,520.6hz. figure 4. multiplexer sequence with neutral channel and remote sensors ck32 mux st at e0 1 2 3 45 settle multiplexer frame mux_div[3:0] = 6 conversions s cross mux_sync s in unused unused va vb vc downloaded from: http:///
maxim integrated 24 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com note that figure 4 only shows the currents that pass through the 71m6543ft/ht/gt/ght multiplexer, and does not show the currents that are copied directly into ce ram from the remote sensors (see figure 3 ), which are sampled during the second half of the multiplexer frame. the two unused conversion slots shown are necessary to produce the desired 2,520.6hz sample rate. the multiplexer sequence shown in figure 5 corresponds to the ct configuration shown in figure 2 . since in this case all current sensors are locally connected to the 71m6543ft/ht/gt/ght, all currents are routed through the multiplexer, as seen in figure 2 . for this multiplexer sequence, the frame duration is 15 ck32 cycles (where ck32 = 32,768hz), therefore, the resulting sample rate is 32,768 hz/15 = 2,184.5hz. delay compensation when measuring the energy of a phase (i.e., wh and varh) in a service, the voltage and current for that phase must be sampled at the same instant. otherwise, the phase difference, , introduces errors. delay delay t 360 t f 360 t ?= ?= ?? where f is the frequency of the input signal, t = 1/f and t delay is the sampling delay between current and voltage. tradition ally, sampling is accomplished by using two a/d converters per phase (one for voltage and the other one for current) controlled to sample simultaneously. our single converter technology, however, ex ploits the 32-bit signal processing capability of its ce to implement con - stant delay allpass filters. the allpass filter corrects for the conversion time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed a/d converter. the constant delay allpass filter provides a broad-band delay 360 C , which is precisely matched to the differ- ence in sample time between the voltage and the current of a given phase. this digital filter does not affect the amplitude of the signal, but provides a precisely controlled phase response. the recommended adc multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle relative to the current. the delay compensation implemented in the ce aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., 360), then routing the voltage samples through the allpass filter, thus delaying the voltage samples by 360o - , resulting in the residual phase error between the current and its corresponding voltage of b C . the residual phase error is negligible, and is typically less than 1.5 milli-degrees at 100hz, thus it does not contribute to errors in the energy measurements. when using remote sensors, the ce performs the same delay compensation described above to align each volt - age sample with its corresponding current sample. even though the remote current samples do not pass through the 71m654xt multiplexer, their timing relationship to their corresponding voltages is fixed and precisely known. figure 5. multiplexer sequence with neutral channel and current transformers ck32 mux stat e0 1234 5 mux_div[3:0] = 7 conversions settle multiplexer frame s cross mux_sync s 6 ia va ib vb ic vc in downloaded from: http:///
maxim integrated 25 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 1. adc input configuration adc preampliier the adc preamplifier is a low-noise differential ampli - fier with a fixed gain of 8 available only on the iadc0- iadc1 sensor input pins. a gain of 8 is enabled by setting pre_e = 1. when disabled, the supply current of the preamplifier is < 10 na and the gain is unity. with proper settings of the pre_e and diffa_e (i/o ram 0x210c[4]) bits, the preamplifier can be used whether or not differen - tial mode is selected. for best performance, the differential mode is recommended. in order to save power, the bias current of the preamplifier and adc is adjusted according to the adc_div control bit (i/o ram 0x2200[5]). analog-to-digital converter (adc) a single 2nd-order delta-sigma adc digitizes the voltage and current inputs to the device. the resolution of the adc, including the sign bit, is 21 bits (fir_len[1:0] = 1), or 22 bits (fir_len[1:0] = 2). initiation of each adc conversion is controlled by mux_ ctrl internal circuit. at the end of each adc conversion, the fir filter output data is stored into the ce ram loca - tion determined by the multiplexer selection. fir data is stored lsb justified, but shifted left 9 bits. fir filter the finite impulse response filter is an integral part of the adc and it is optimized for use with the multiplexer. the purpose of the fir filter is to decimate the adc output to the desired resolution. at the end of each adc conver - sion, the output data is stored into the fixed ce ram location determined by the multiplexer selection. voltage references a bandgap circuit provides the reference voltage to the adc. the v ref band-gap amplifier is chopper-stabilized to remove the dc offset voltage. this offset voltage is the most significant long-term drift mechanism in voltage ref - erence circuits.isolated sensor interface nonisolating sensors, such as shunt resistors, can be connected to the inputs of the 71m654x via a combina - tion of a pulse transformer and a 71m6x03 isolated sen - sor interface. the 71m6x03 receives power directly from the 71m654xt through a pulse transformer and does not require a dedicated power supply circuit. the 71m6x03 establishes 2-way communication with the 71m654xt, supplying current samples and auxiliary information such as sensor temperature via a serial data stream. up to three 71m6x03 isolated sensors can be supported by the 71m6543ft/ht/gt/ght. when a remote sen - sor interface is enabled, the two analog current inputs become reconfigured as a digital remote sensor interface. each 71m6x03 isolated sensor consists of the following building blocks: ? power supply for power pulses received from the 71m654xt ? digital communications interface ? shunt signal preamplifier ? delta-sigma adc converter with precision bandgap reference (chopping amplifier) ? temperature sensor ? fuse system containing part-specific information pin required setting comment iadc0 diffx_e = 1 differential mode must be selected with diffx_e = 1. the adc results are stored in adc0 and adc1 is not disturbed. iadc1iadc2 diffx_e = 1 or rmt_e = 1 for locally connected sensors the differential input must be enabled. for the remote sensor rmt_e must be set. adc results are stored in adc2 and adc3 is not disturbed. iadc3iadc4 diffx_e = 1 or rmt_e = 1 for locally connected sensors the differential input must be enabled. for the remote sensor rmt_e must be set. adc results are stored in adc4 and adc5 is not disturbed. iadc5iadc6 diffx_e = 1 or rmt_e = 1 for locally connected sensors the differential input must be enabled. for the remote sensor rmt_e must be set. adc results are stored in adc6 and adc7 is not disturbed. iadc7 vadc8 phase a voltage. single ended mode only. adc result stored in adc8. vadc9 phase b voltage. single ended mode only. adc result stored in adc9. vadc10 phase a voltage. single ended mode only. adc result stored in adc10. downloaded from: http:///
maxim integrated 26 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com during an ordinary multiplexer cycle, the 71m654xt inter - nally determines which other channels are enabled. at the same time, it decimates the modulator output from the 71m6x03 isolated sensors. each result is written to ce ram during one of its ce access time slots. the adc of the 71m6x03 derives its timing from the power pulses generated by the 71m654xt and as a result, oper - ates its adc slaved to the frequency of the power pulses. the generation of power pulses, as well as the commu - nication protocol between the 71m654xt and 71m6x03 isolated sensor is au tomatic and transparent to the user. the 71m654xt can read data and status from, and can write control information to the 71m6x03 isolated sensor. with hardware and trim-related information on each connected 71m6x03 isolated sensor available to the 71m6543ft/ht/gt/ght, the mpu can implement temperature compensation of the energy measurement based on the individual temperature characteristics of the 71m6x03 isolated sensor. digital computation engine (ce) the ce, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. the ce calculations and processes include: ? multiplication of each current sample with its associ - ated voltage sample to obtain the energy per sample (when multiplied with the constant sample time). ? frequency-insensitive delay cancellation on all four channels (to compensate for the delay bet ween sam - ples caused by the multiplexing scheme). ? 90 phase shifter (for var calculations). ? pulse generation. ? monitoring of the input signal frequency (for frequency and phase information). ? monitoring of the input signal amplitude (for sag detec - tion). ? scaling of the processed samples based on calibration coefficients. ? scaling of samples based on temperature compensa - tion information. meter equations the 71m6543ft/ht/gt/ght provides hardware assis - tance to the ce in order to support various meter equa - tions. the compute engine firmware for industrial con - figurations can implement the equations listed in table 2 . equ[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering. real-time monitor the ce contains a real-time monitor (rtm), which can be programmed to monitor four selectable xram locations at full sample rate. the four monitored locations are serially output to the tmuxout pin via the digital output multi - plexer at the beginning of each ce code pass. the rtm can be enabled and disabled with control bit rtm_e. the rtm output is clocked by cktest. each rtm word is clocked out in 35 ckce cycles (1 ckce cycle is equiva - lent to 203ns) and contains a leading flag bit.pulse generators the 71m6543ft/ht/gt/ght provides four pulse genera - tors, vpulse, wpulse, xpulse and ypulse, as well as hardware support for the vpulse and wpulse pulse generators. the pulse generators can be used to output ce status indicators (for example, voltage sag) to dio pins. all pulses can be configured to generate interrupts to the mpu. the polarity of the pulses may be inverted with control bit pls_inv. when this bit is set, the pulses are active high, rather than the more usual active low. pls_inv inverts all four pulse outputs. table 2. inputs selected in multiplexer cycles note: only equ = 5 is supported by currently available ce code versions for the 71m6543ft/ht/gt/ght. contact your maxim integrated representative for ce codes that support equations 2, 3 and 4. equ description wh and varh formula recommended multiplexer sequence element 0 element 1 element 2 2 2-element, 3w 3ph delta va x ia va x ib n/a ia va ib vb 3 2-element, 4w 3ph delta va (ia-ib)/2 vc x ic n/a ia va ib vb ic vc 4 2-element, 4w 3ph wye va (ia-ib)/2 vb (ic-ib)/2 n/a ia va ib vb ic vc 5 3-element, 4w 3ph wye va x ia vb x ia vc x ic ia va ib vb ic vc (id) downloaded from: http:///
maxim integrated 27 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 3. ckmpu clock frequencies the function of each pulse generator is determined by the ce code and the mpu code must configure the cor - responding pulse outputs in agreement with the ce code. for example, standard ce code produces a mains zero- crossing pulse on xpulse and a sag pulse on ypulse. a common use of the zero-crossing pulses is to gener - ate interrupt in order to drive real-time clock software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. a common use for the sag pulse is to generate an interrupt that alerts the mpu when mains power is about to fail, so that the mpu code can store accumulated energy and other data to eeprom before the v v3p3sys supply voltage actually drops. xpulse and ypulse pulses generated by the ce may be exported to the xpulse and ypulse pulse output pins. pins segdio6 and segdio7 are used for these pulses, respectively. generally, the xpulse and ypulse outputs can be updated once on each pass of the ce code. vpulse and wpulse by default, wpulse emits a pulse proportional to real energy consumed, and vpulse emits a pulse propor - tional to reactive energy. during each ce code pass the hardware stores exported wpulse and vpulse sign bits in an 8-bit fifo and sends the buffered sign bits to the output pin at a specified, known interval. this permits the ce code to calculate the vpulse and wpulse outputs at the beginning of its code pass and to rely on hardware to spread them over the multiplexer frame. 80515 mpu core the 71m6543ft/ht/gt/ght includes an 80515 mpu (8-bit, 8051-compatible) that processes most instructions in one clock cycle: a 4.9mhz clock results in a process - ing throughput of 4.9 mips. the 80515 architecture eliminates redundant bus states and im plements parallel execution of fetch and execution phases. normally, a machine cycle is aligned with a memory fetch, there fore, most of the 1-byte instructions are performed in a single machine cycle (mpu clock cycle). this leads to an 8x average performance im prove ment (in terms of mips) over the 8051 device running at the same clock frequency. the ckmpu frequency is a function of the mck clock (19.6608mhz) divided by the mpu clock divider which is set in the i/o ram control field mpu_div[2:0]. actual processor clocking speed can be adjusted to the total pro- cessing demand of the application (metering calculations, amr management, memory management, lcd driver management and i/o management) using mpu_div[2:0], as shown in table 3 . memory organization and addressing the 80515 mpu core incorporates the harvard archi - tecture with separate code and data spaces. memory organization in the 80515 is similar to that of the industry standard 8051. there are three memory areas: program memory (flash, shared by mpu and ce), external ram (data ram, shared by the ce and mpu, configuration or i/o ram), and internal data memory (internal ram). program memory the 80515 can address up to 64kb of program memory space (0x0000 to 0xffff). program memory is read when the mpu fetches instructions or performs a movc operation. after reset, the mpu starts program execution from pro - gram memory location 0x0000. the lower part of the pro - gram memory includes reset and interrupt vectors. the interrupt vectors are spaced at 8-byte in tervals, starting from code space location 0x0003. mpu external data memory (xram) both internal and external memory is physically located on the 71m654xt device. the ex ternal mem ory referred in this documentation is only external to the 80515 mpu core. 3kb of ram starting at address 0x0000 is shared by the ce and mpu. the ce normally uses the first 1kb, leav - ing 2kb for the mpu. different versions of the ce code use varying amounts. consult the documentation for the specific code version being used for the exact limit. movx addressing there are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to the external data ram: mpu_div [2:0] ckmpu frequency 000 4.9152mhz 001 2.4576mhz 010 1.2288mhz 011 614.4khz 100 307.2khz 101 110 111 downloaded from: http:///
maxim integrated 28 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 4. memory map * memory size depends on ic. see the on-chip resources section for details. ? movx a,@ri: the contents of r0 or r1 in the current register bank provide the eight low-order address bits with the eight high-order bits specified by the pdata sfr. this method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data ram. ? movx a,@dptr: the data pointer generates a 16-bit address. this form is faster and more efficient when accessing very large data arrays (up to 64kb) since no additional instructions are needed to set up the eight high ordered bits of the address. it is possible to mix the two movx types. this provides the user with four separate data pointers, two with direct access and two with paged access, to the entire external memory range. dual data pointer the dual data pointer accelerates the block moves of data. the standard dptr is a 16-bit register that is used to address external memory or peripherals. in the 80515 core, the standard data pointer is called dptr, the sec - ond data pointer is called dptr1. the data pointer select bit, located in the lsb of the dps register, chooses the active pointer. dptr is selected when dps[0] = 0 and dptr1 is selected when dps[0] = 1. the user switches between pointers by toggling the lsb of the dps register. the values in the data pointers are not affected by the lsb of the dps register. all dptr related instructions use the currently selected dptr for any activity. an alternative data pointer is available in the form of the pdata register (sfr 0xbf), sometimes referred to as usr2). it defines the high byte of a 16-bit address when reading or writing xdata with the instruction movx a,@ ri or movx @ri,a. internal data memory map and access the internal data memory provides 256 bytes (0x00 to 0xff) of data memory. the internal data memory address is always 1 byte wide. the special function registers (sfr) occupy the upper 128 bytes. the sfr area of internal data memory is available only by direct addressing . indirect address - ing of this area accesses the upper 128 bytes of internal ram. the lower 128 bytes contain working registers and bit addressable memory. the lower 32 bytes form four banks of eight registers (r0-r7). two bits on the program memory status word (psw, sfr 0xd0) select which bank is in use. the next 16 bytes form a block of bit address - able memory space at addresses 0x00-0x7f. all of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. table 5. internal data memory map address (hex) memory technology memory type name typical usage memory size (bytes) 0000-ffff (64k) 0000-1ffff (128k) flash memory nonvolatile program memory for mpu and ce mpu program and nonvolatile data 128/64k* ce program (on 1kb boundary) 3k max 0000-0bff static ram volatile external ram (xram) shared by ce and mpu 5k* 2000-27ff static ram volatile coniguration ram (i/o ram) hardware control 2k 2800-287f static ram nonvolatile (battery) coniguration ram (i/o ram) battery-buffered memory 128 0000-00ff static ram volatile internal ram part of 80515 core 256 address range direct addressing indirect addressing 0x80 0xff special function registers (sfrs) ram 0x30 0x7f byte addressable area 0x20 0x2f bit addressable area 0x00 0x1f register banks r0r7 downloaded from: http:///
maxim integrated 29 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 6. special function register map special function registersonly a few addresses in the sfr memory space are occupied; other addresses are unim plemented. a read access to unimplemented addresses returns undefined data, while a write access has no effect. sfrs specific to the 71m654xt are shown in bold print on a shaded field. the registers at 0x80, 0x88, 0x90, etc., are bit address - able, all others are byte addressable. timers and counters the 71m6543ft/ht/gt/ght contains two 16-bit timer/ counter registers: timer 0 and timer 1. these registers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods of the mpu clock. in counter mode, the register is incremented when the falling edge is observed at the corresponding input signal t0 or t1 (t0 and t1 are the timer gating inputs derived from certain dio pins, see 2.5.8 digital i/o). since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (ckmpu). there are no restrictions on the duty cycle, how ever to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. the tmod register is used to select the appro - priate mode. the timer/counter operation is controlled by the tcon register. bits tr1 and tr0 in the tcon regis - ter start their associated timers when set. table 7. timers/counters mode description hex/ bin bit addressable byte addressable bin/ hex x000 x001 x010 x011 x100 x101 x110 x111 f8 intbits vstat rcmd spi_cmd ff f0 b f7 e8 iflags ef e0 a e7 d8 wdcon df d0 psw d7 c8 t2con cf c0 ircon c7 b8 ien1 ip1 s0relh s1relh pdata bf b0 p3 (dio12:15) flsh_ctl flsh_ bank flsh_ pgadr b7 a8 ien0 ip0 s0rell af a0 p2 (dio8:11) a7 98 s0con s0buf ien2 s1con s1buf s1rell eedata eectrl 9f 90 p1 (dio4:7) dps flsh_ erase 97 88 tcon tmod tl0 tl1 th0 th1 ckcon 8f 80 p0 (dio0:3) sp dpl dph dpl1 dph1 pcon 87 m1 m0 mode function 0 0 mode 0 13-bit counter/timer mode with 5 lower bits in the tl0 or tl1 register and the remaining 8 bits in the th0 or th1 register (for timer 0 and timer 1, respectively). the 3 high order bits of tl0 and tl1 are held at zero. 0 1 mode 1 16-bit counter/timer mode. 1 0 mode 2 8-bit auto-reload counter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented every machine cycle. when tlx overlows, a value from thx is copied to tlx. 1 1 mode 3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, timer 0 acts as two independent 8-bit timer/counters. downloaded from: http:///
maxim integrated 30 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 8. generic 80515 sfrs: location and reset values name address reset value description p0 0x80 0xff port 0 sp 0x81 0x07 stack pointer dpl 0x82 0x00 data pointer low 0 dph 0x83 0x00 data pointer high 0 dpl1 0x84 0x00 data pointer low 1 dph1 0x85 0x00 data pointer high 1 pcon 0x87 0x00 uart speed control tcon 0x88 0x00 timer/counter control tmod 0x89 0x00 timer mode control tl0 0x8a 0x00 timer 0, low byte tl1 0x8b 0x00 timer 1, high byte th0 0x8c 0x00 timer 0, low byte th1 0x8d 0x00 timer 1, high byte ckcon 0x8e 0x01 clock control (stretch = 1) p1 0x90 0xff port 1 dps 0x92 0x00 data pointer select register s0con 0x98 0x00 serial port 0, control register s0buf 0x99 0x00 serial port 0, data buffer ien2 0x9a 0x00 interrupt enable register 2 s1con 0x9b 0x00 serial port 1, control register s1buf 0x9c 0x00 serial port 1, data buffer s1rell 0x9d 0x00 serial port 1, reload register, low byte p2 0xa0 0xff port 2 ien0 0xa8 0x00 interrupt enable register 0 ip0 0xa9 0x00 interrupt priority register 0 s0rell 0xaa 0xd9 serial port 0, reload register, low byte p3 0xb0 0xff port 3 ien1 0xb8 0x00 interrupt enable register 1 ip1 0xb9 0x00 interrupt priority register 1 s0relh 0xba 0x03 serial port 0, reload register, high byte s1relh 0xbb 0x03 serial port 1, reload register, high byte pdata 0xbf 0x00 high address byte for movx@ri - also called usr2 ircon 0xc0 0x00 interrupt request control register t2con 0xc8 0x00 polarity for int2 and int3 psw 0xd0 0x00 program status word wdcon 0xd8 0x00 baud rate control register (only wdcon[7] bit used) a 0xe0 0x00 accumulator b 0xf0 0x00 b register downloaded from: http:///
maxim integrated 31 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 9. external mpu interrupts interrupts the 80515 provides 11 interrupt sources with four priority levels. each source has its own interrupt request flag(s) located in a special function register (tcon, ircon, and scon). each interrupt requested by the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the ien0, ien1, and ien2. referring to figure 12 , interrupt sources can origi - nate from within the 80515 mpu core (referred to as internal sources) or can originate from other parts of the 71m654xt soc (referred to as external sources). there are seven external interrupt sources, (ex0-ex6). interrupt overview when an interrupt occurs, the mpu vectors to the prede - termined address. once the interrupt service has begun, it can be interrupted only by a higher priority interrupt. the interrupt service is terminated by a return from interrupt instruction (reti). when a reti instruction is executed, the processor returns to the instruction that would have been next when the interrupt occurred. when the interrupt condition occurs, the processor also indicates this by setting a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each inter - rupt flag is sampled once per machine cycle, and then samples are polled by the hardware. if the sample indi - cates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. on the next instruc - tion cycle, the interrupt is acknowledged by hardware forcing an lcall to the appropriate vector address, if the following conditions are met: ? no interrupt of equal or higher priority is already in progress. ? an instruction is currently being executed and is not completed. ? the instruction in progress is not reti or any write access to the registers ien0, ien1, ien2, ip0 or ip1. the following sfr registers control the interrupt functions: ? the interrupt enable registers: ien0, ien1 and ien2. ? the timer/counter control registers, tcon and t2con. ? the interrupt request register, ircon. ? the interrupt priority registers: ip0 and ip1. external mpu interrupts the seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in other parts of the 71m654xt, for example the ce, dio, rtc, or eeprom interface. the polarity of interrupts 2 and 3 is programmable in the mpu via the i3fr and i2fr bits in t2con (sfr 0xc8). interrupts 2 and 3 should be programmed for falling sensitivity (i3fr = i2fr = 0). the generic 8051 mpu literature states that interrupts 4 through 6 are defined as rising-edge sensitive. thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in table 9 . external interrupt 0 and 1 can be mapped to pins on the device using dio resource maps. on-chip resources flash memory the device includes 128kb (71m6543gt/ght) or 64kb (71m6543ft/ht) of on-chip flash memory. the flash memory primarily contains mpu and ce program code. it also contains images of the ce ram and i/o ram. on power-up, be fore enabling the ce, the mpu copies these images to their respective locations. flash space allocated for the ce program is limited to 4096 16-bit words (8kb). the ce program must begin on a 1kb boundary of the flash address space. the ce_lctn[6:0] (71m6543gt/ght) or ce_lctn[5:0] (71m6543ft/ht) field defines where in flash the ce code external interrupt connection polarity flag reset 0 digital i/o (ie0) programmable automatic 1 digital i/o (ie1) programmable automatic 2 ce_pulse (ie_xpulse, ie_ypulse, ie_wpulse, ie_vpulse) rising manual 3 ce_busy (ie3) falling automatic 4 vstat (vstat[2:0] changed) (ie4) rising automatic 5 eeprom busy (falling), spi (rising) (ie_eex, ie_spi) manual 6 xfer_busy (falling), rtc_1sec, rtc_1min, rtc_t, tc_temp (ie_xfer, ie_rtc1s, ie_rt1m, ie_rtct) falling manual downloaded from: http:///
maxim integrated 32 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 10. flash banks resides. the address of the ce program is 0bxxxx xx00 0000 0000, where xxxx xx represents one of the 64 1kb pages at which the ce program begins. flash memory can be accessed by the mpu and the ce for reading, and by the spi interface for reading or writing. the program memory of the 71m6543gt/71m6543ght consists of a fixed lower bank area of 32 kb addressable at 0x0000 to 0x7fff plus an upper bank area of 32 kb, addressable at 0x8000 to 0xffff. the upper bank area is banked using the i/o ram flsh_bank register as follows. note that when flsh_bank[1:0] = 00, the upper bank area is the same as the lower bank area ( table 10 ). the flash memory page address register flsh_ pgadr[6:0] (sfr b7[7:1]) points to an address in the 71m6543gt/71m6543ght program address space. this address in the 71m6543gt/71m6543ght program address space can refer to different flash memory address - es, depending on the setting of the flsh_bank[1:0] bits. the ce location register (ce_lctn[6:0]), on the other hand, points directly to an address in the flash memory and is not affected by the flsh_bank[1:0] bits. when the secure bit (sfr b2[6]) is set to a 1, page erase of certain flash memory pages is blocked. these pages are page 0 (flash memory address range 0x00000 C0x003ff) and all pages between the start of the ce program (ce_lctn[6:0]) and flash memory address 0x1ffff. while operating in spi flash mode (sfm), spi single- byte transactions are used to write to flsh_bank[1:0]. during a spi single-byte transaction, spi_cmd[1:0] overwrites the contents of flsh_bank[1:0]. this allows access to the entire 128kb flash memory while operating in sfm on the 71m6543gt/71m6543ght. mpu/ce ram the 71m6543ft/ht/gt/ght includes 5kb of static ram memory on-chip (xram) plus 256 bytes of internal ram in the mpu core. the static ram is used for data storage for both mpu and ce operations. i/o ram the i/o ram can be seen as a series of hardware reg - isters that control basic hardware functions. i/o ram address space starts at 0x2000. the 71m6543ft/ht/gt/ght includes 128 bytes nv ram memory on-chip in the i/o ram address space (addresses 0x2800 to 0x287f). this memory section is supported by the voltage applied at v bat_rtc and the data in it are preserved in brn, lcd, and slp modes as long as the voltage at v bat_rtc is within specification. crystal oscillator the oscillator drives a standard 32.768khz tuning-fork crystal. this type of crystal is accurate and does not require a high-current oscillator circuit. the oscillator power dissipation is very low to maximize the lifetime of the v bat_rtc battery. oscillator calibration can improve the accuracy of both the rtc and metering. pll timing for the device is derived from the 32,768hz crystal oscillator. the oscillator output is routed to a phase-locked loop (pll). the pll multiplies the crystal frequency by 600 to produce a stable 19.6608mhz clock frequency. this is the master clock (mck), and all on-chip timing, except for the rtc clock, is derived from mck. the master clock can operate at either 19.66mhz or 6.29mhz depending on the pll_fast bit. the mpu clock frequency ckmpu is determined by another divider controlled by the i/o ram control field mpu_div[2:0] and can be set to mck x 2 -(mpu_div+2) , where mpu_div[2:0] may vary from 0 to 4. the 71m654xt v v3p3sys supply current is reduced by reducing the mpu clock frequency. when the ice_e pin is high, the circuit also generates the 9.83mhz clock for use by the emulator. the two general-purpose counter/timers contained in the mpu are clocked by ckmpu. the pll is only turned off in slp mode. flsh_bank[1:0] address range for lower bank (0x0000C0x7fff) address range for upper bank (0x8000C0x7fff) 00 0x0000C0x7fff 0x0000C0x7fff 01 0x0000C0x7fff 0x8000C0x7fff 10 0x0000C0x7fff 0x10000C0x17ffff 11 0x0000C0x7fff 0x18000C0x1ffff downloaded from: http:///
maxim integrated 33 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com when the part is waking up from slp or lcd modes, the pll is turned on in 6.29mhz mode, and the pll fre - quency is not be accurate until the pll_ok flag becomes active. due to potential overshoot, the mpu should not change the value of pll_fast until pll_ok is true. real-time clock (rtc) the real-time clock is driven directly by the crystal oscillator and is powered by either the v v3p3sys pin or the v bat_rtc pin, depending on the v3ok internal bit. the rtc consists of a counter chain and a set of output registers. the counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year. the chain registers are supported by a shadow register that facilitates read and write operations. rtc trimming the rtc accuracy can be trimmed by means of a digital trimming mechanism that affects only the rtc. either or both of these adjustment mechanisms can be used to trim the rtc. the 71m6543ft/ht/gt/ght can also be configured to regularly measure die temperature, including in slp and lcd modes and while the mpu is halted. if enabled, the temperature information is automatically used to correct for the temperature variation of the crystal. a quadratic equation is used to compute the temperature correction factors. the temperature is passed both to the quadratic calcula - tion block and to a range check block. if the temperature exceeds the limits established in the smin, smax and sfilt registers when a range checking is enabled, a wake or an interrupt event is posted. the quadratic calculation block computes the position on the inverse parabolic curve that is characteristic for tuning fork crystals based on the known and t 0 values for the crystal (these are published by the crystal manufacturer and are relatively consistent for a particular crystal type). finally, the absolute frequency error is added or subtract - ed from the computed value, and the final result is used to compensate the frequency of the crystal. rtc interrupts the rtc generates interrupts each second and each minute. these interrupts are called rtc_1sec and rtc_1min. in addition, the rtc functions as an alarm clock by generating an interrupt when the minutes and hours registers both equal their respective target counts as defined in the alarm registers. the alarm clock inter - rupt is called rtc_t. all three interrupts appear in the mpus external interrupt 6. temperature sensor the 71m654xt includes an on-chip temperature sensor for determining the temperature of its bandgap re ference. the primary use of the temperature data is to determine the magnitude of compensation re quired to offset the ther - mal drift in the system for the compensa tion of current, voltage and energy measurement and the rtc. see the metrology temperature compensation . the 71m654xt uses a dual-slope temperature measure - ment technique that is operational in slp and lcd mode, as well as brn and msn modes. this means that the temperature sensor can be used to compensate for the frequency variation of the crystal, even in slp mode while the mpu is halted. in msn and brn modes, the temperature sensor is awakened on command from the mpu by setting the temp_start control bit. the mpu must wait for the temp_start bit to clear before reading stemp[15:0] and before setting the temp_start bit once again. in slp and lcd modes, it is awakened at a regular rate set by temp_per[2:0]. the result of the temperature measurement can be read from stemp[15:0]. typically, only eleven bits are signifi - cant, the remaining high-order bits reflecting the sign of the temperature relative to 0c. battery monitor the 71m654xt temperature measurement circuit can also monitor the batteries at the v bat and v bat_rtc pins. the battery to be tested (i.e., v bat or v bat_rtc pin) is selected by temp_bsel. when temp_bat is set, a battery measurement is performed as part of each temperature measurement. the value of the battery reading is stored in register bsense[7:0]. the battery voltage can be calculated by using the formula in the battery monitor section of the electrical characteristics table. in msn mode, a 100a de-passivation load can be applied to the selected battery (i.e., selected by the temp_bsel bit) by setting the bcurr bit. battery impedance can be measured by taking a battery measurement with and without bcurr. regardless of the bcurr bit setting, the battery load is never applied in brn, lcd, and slp modes. downloaded from: http:///
maxim integrated 34 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com digital i/o and lcd segment drivers the 71m6543ft/ht/gt/ght combines most dio pins with lcd segment drivers. each seg/dio pin can be configured as a dio pin or as a segment (seg) driver pin. on reset or power-up, all dio pins are dio inputs until they are configured as desired under mpu control. the pin function can be configured by the i/o ram registers lcd_mapn. setting the bit corresponding to the pin in lcd_mapn to 1 configures the pin for lcd, setting lcd_mapn to 0 configures it for dio. once a pin is configured as dio, it can be configured independently as an input or output. the pb pin is a dedi - cated digital input and is not part of the segdio system. some pins (segdio2 through segdio11 and pb) can be routed to internal logic such as the interrupt control - ler or a timer channel. this routing is independent of the direction of the pin, so that outputs can be configured to cause an interrupt or start a timer. a total of 32 combined seg/dio pins plus 5 seg outputs are available for the 71m6543ft/ht/gt/ght. these pins can be categorized as follows: 17 combined seg/dio segment pins: ? segdio4segdio5 (2 pins) ? segdio9segdio14 (6 pins) ? segdio19segdio25 (7 pins) ? segdio44segdio45 (2 pins) 15 combined seg/dio segment pins shared with other functions: ? segdio0/wpulse, segdio1/vpulse (2 pins) ? segdio2/sdck, segdio3/sdata (2 pins) ? segdio6/xpulse, segdio7/ypulse (2 pins) ? segdio8/di (1 pin) ? segdio26/com5, segdio27/com4 (2 pins) ? segdio36/spi_cszsegdio39/spi_cki (4 pins) ? segdio51/opt_tx, segdio55/opt_rx (2 pins) 5 dedicated seg segment pins are available: ? ice inteface pins: seg48/e_rxtx, seg49/e_tclk, seg50/e_rst (3 pins) ? test port pins: seg46/tmux2out, seg47/tmuxout (2 pins) there are four dedicated common segment outputs (com0com3) plus the two additional shared common segment outputs that are listed under combined seg/dio shared pins (segdio26/com5, segdio27/com4). thus, in a configuration where none of these pins are used as dios, there can be up to 37 lcd segment pins with 4 commons, or 35 lcd segment pins with 6 com - mons. and in a configuration where lcd segment pins are not used, there can be up to 32 dio pins. lcd drivers the lcd drivers are grouped into up to six commons (com0 C com5) and up to 56 segment drivers. the lcd interface is flexible and can drive 7-segment digits, 14-segments digits or annunciator symbols. lcd voltage can be taken from the v lcd pin or the v v3p3sys pin. a contrast dac regulates v lcd from either v bat or v v3p3sys . the lcd system has the ability to drive up to six seg - ments per seg driver. if the display is configured with six back planes, the 6-way multiplexing minimizes the num - ber of seg pins required to drive a display. this maxi - mizes the number of dio pins available to the application. if 5-state multiplexing is selected, segdio27 is converted to com4. if 6-state multiplexing is selected, segdio26 is converted to com5. the lcd_on and lcd_blank bits are an easy way to either blank the lcd display or to turn all segments on. neither bit affects the contents of the lcd data stored in the lcdseg_dio[ ] registers. in comparison, lcd_rst (i/o ram 0x240c[2]) clears all lcd data to zero. lcd_ rst affects only pins that are configured as lcd. the lcd can be driven in static, ? bias, and ? bias modes. note that com pins that are not required in a specific mode maintain a segment off state rather than gnd, vcc, or high impedance. the segment drivers segdio22 and segdio23 can be configured to blink at either 0.5 hz or 1 hz. the blink rate is controlled by lcd_y. there can be up to six segments connected to each of these driver pins. the i/o ram fields lcd_blkmap22[5:0] and lcd_blkmap23[5:0] identify which pixels, if any, are to blink. lcd_blkmap22[5:0] and lcd_blkmap23[5:0] are nonvolatile. the lcd bias may be compensated for temperature using the lcd_dac[4:0] field. the bias may be adjusted from 1.4 v below the 3.3 v supply (v v3p3sys in msn mode and v bat in brn and lcd modes). when the lcd_dac[4:0] field is set to 000, the dac is bypassed and powered down. this can be used to reduce current in lcd mode. the 71m6543ft/ht/gt/ght has 56 lcd driver pins available, and can drive up to 336 segments. downloaded from: http:///
maxim integrated 35 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 6. typical lcd waveforms static (lcd_mode=100) com0com1 com2 com3 com4com5 seg_on seg_off (1/2)(1/2) (1/2) (1/2) (1/2) 1/3 bias, 3 st at es (lcd_mode = 011 ) com0com1 com2 com3 com4com5 seg_on seg_off (2/3) 012 (1/3) 1/2 bias, 3 st at es (lcd_mode = 011 ) com0com1 com2 com3 com4com5 seg_on seg_off (1/2)(1/2) (1/2) 012 1/3 bias, 6 st at es (lcd_mode = 110 ) com0com1 com2 com3 com4com5 seg_on seg_off 012 3 45 1/2 bias, 2 s tat es (lcd_mode = 010 ) com0com1 com2 com3 com4com5 seg_on seg_off (1/2)(1/2) (1/2) (1/2) 01 1/3 bias, 4 st at es (lcd_mode = 000 ) com0com1 com2 com3 com4com5 seg_on seg_off 012 3 t downloaded from: http:///
maxim integrated 36 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com square wave output the 71m654xt includes a square wave generator that can be configured to present a square wave on the segdio15 pin. this square wave can be used as a clock to drive other devices and peripherals. the output is enabled by setting the out_sqe bit. the output frequency can then be selected by setting the out_sq[1:0] bits. eeprom interface the 71m654xt provides hardware support for both two- pin (i 2 c) and three-wire (microwire) eeproms. two-pin eeprom interface the two-pin serial interface is multiplexed onto the segdio2 (sdck) and segdio3 (sdata) pins. configure the interface for two-pin mode by setting dio_eex[1:0] = 01. the mpu communicates with the interface through the sfr registers eedata and eectrl. to write a byte of data to the eeprom the mpu places the data in eedata and then writes the transmit code to eectrl. this initiates the transmit operation which is finished when the busy bit falls. int5 is also asserted when busy falls. the mpu can then check the rx_ack bit to see if the eeprom acknowledged the trans mission. a byte is read by writing the receive command to eectrl and waiting for the busy bit to fall. upon com - pletion, the received data is in eedata. the serial trans - mit and receive clock is 78khz during each transmission, and then holds in a high state until the next transmission. the two-pin interface handles protocol details. the mpu can command the interface to issue a start, a repeated start and a stop condition, and it can manage the transmit - ted ack status as well. three-wire eeprom interface the three-wire interface supports standard microwire (single data pin with clock and select pins) or a subset of spi (separate di and do pins with clock and select pins). microwire is selected by setting dio_eex[1:0] = 10. in this mode, eectrl selects whether the interface is sending or receiving, and eight bits of data are transferred in each transaction. in this configuration, segdio2 is configured for clock, and segdio3 is configured for data. when separate di/do pins are selected (dio_eex[1:0] = 11) the interface operates as a subset of spi. only spi modes 0 or 3 are supported. in this configuration, segdio3 is do and segdio8 is di. uart the 71m6543ft/ht/gt/ght include a uart (uart0) that can be programmed to communicate with a variety of amr modules and other external devices. a second uart (uart1) is connected to the optical port. the 80515 only supports two uarts, but meters occasion - ally need three. the 71m654xt tries to help in two ways. first, as shown in figure 7 , the 71m654xt can be config - ured to switch the optical uart to dios 5 and 17 by setting umux_sel (i/o ram 0x2456[4]) to 1. this is useful when a conventional uart can appear by command at different pins. the dios must not be configured as lcd outputs. also, as shown in figure 7 , the 71m654xt can also be configured to drive the opti7al uart with dio signal in a bit banged configuration. when control bit opt_bb (i/o ram 0x2022[0]) is set, the optical port is driven by dio5 and the segdio5 pin is driven by uart1_tx. this con - figuration is typically used when the two dedicated uarts must be connected to high speed clients and a slower optical uart is permissible. spi slave port the spi slave port communicates directly with the mpu data bus and is able to read and write data ram and i/o ram locations. it is also able to send commands to the mpu. the interface to the slave port consists of the spi_csz, spi_cki, spi_di and spi_do pins. these pins are multi plexed with the combined dio/lcd segment driver pins segdio36 to segdio39. additionally, the spi interface allows flash memory to be read and to be programmed. to facilitate flash pro- gramming, cycling power or asserting reset causes the spi port pins to default to spi mode. the spi port is disabled by clearing the spi_e bit. possible applications for the spi interface are: ? an external host reads data from ce locations to obtain metering information. this can be used in applications where the 71m654xt function as a smart front-end with preprocessing capability. since the addresses are in 16-bit format, any type of xram data can be accessed: ce, mpu, i/o ram, but not sfrs or the 80515-internal register bank. ? a communication link can be established via the spi interface: by writing into mpu memory locations, the external host can initiate and control processes in the 71m654xt mpu. writing to a ce or mpu location normally generates an interrupt, a function that can be downloaded from: http:///
maxim integrated 37 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 7. optical interface (uart1) 1 seg17 internal lcd_segdio17 = 2 lcd_map[17] segdio17 0 1 seg16 lcd_segdio16 = 0 lcd_map[16] segdio16 0 00 1 1 uart1_tx dio17 00 1 1 0 1 1 uart1_rx 1 seg55 lcd_map[55] segdio55/opt_rx v3p3 0 1 dio55 opt_rxinv opt_rxdis varpulse 3 0 1 seg51 lcd_map[51] wpulse 2 dio51 0 opt_txe[1:0] b a en opt_txmod opt_fdc 2 opt_txinv duty mod 1 opt_tx 0 1 seg5 lcd_map[5] opt_txmod = 1 opt_fdc = 2 (25%) opt_txmod = 0 1/38khz a b umux_sel uart1_tx 1 0 1 uart1_tx dio5 opt_bb segdio5/tx2 0 downloaded from: http:///
maxim integrated 38 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com used to signal to the mpu that the byte that had just been written by the external host must be read and processed. data can also be inserted by the external host without generating an interrupt. ? an external dsp can access front-end data gener - ated by the adc. this mode of operation uses the 71m654xt as an analog front-end (afe). ? flash programming by the external host (spi flash mode). spi safe mode sometimes it is desirable to prevent the spi interface from writing to arbitrary ram locations and thus disturb - ing mpu and ce operation. this is especially true in afe applications. for this reason, the spi safe mode was created. in spi safe mode, spi write operations are disabled except for a 16 byte transfer region at address 0x400 to 0x40f. if the spi host needs to write to other addresses, it must use the spi_cmd register to request the write operation from the mpu. spi safe mode is enabled by the spi_safe bit. spi flash mode (sfm) in normal operation, the spi slave interface cannot read or write the flash memory. however, the 71m6543ft/ht/ gt/ght supports a spi flash mode (sfm) which facili - tates initial programming of the flash memory. when in sfm mode, the spi can erase, read, and write the flash memory. other memory elements such as xram and i/o ram are not accessible in this mode. in order to protect the flash contents, several operations are required before the sfm mode is successfully invoked. in sfm mode, n byte reads and dual-byte writes to flash memory are supported. since the flash write operation is always based on a two-byte word, the initial address must always be even. data is written to the 16-bit flash memory bus after the odd word is written. while operating in spi flash mode (sfm), spi single-byte transacations are used to wrtie flsh_bank[1:0]. during an spi single-byte transaction, spi_cmd[1:0] overwrites the contents of flsh_bank[1:0]. this allows access to the entire 128kb flash memory while operating in sfm on the 71m6543gt/ght. in sfm mode, the mpu is completely halted. the 71m6543ft/ht/gt/ght must be reset by the wd timer or by the reset pin in order to exit sfm mode. if the spi port is used for code updates (in lieu of a programmer that uses the ice port), then a code that disables the flash access through spi can potentially lock out flash program updates. hardware watchdog timer an independent, robust, fixed-duration, watchdog timer (wdt) is included in the 71m6543ft/ht/gt/ght. it uses the rtc crystal oscillator as its time base and must be refreshed by the mpu firmware at least every 1.5 sec - onds. when not re freshed on time, the wdt overflows and the part is reset as if the reset pin were pulled high, except that the i/o ram bits are in the same state as after a wake-up from slp or lcd modes. after 4100 ck32 cycles (or 125 ms) following the wdt overflow, the mpu is launched from program address 0x0000. the watchdog timer is also reset when the internal signal wake = 0. test ports two independent multiplexers allow the selection of internal analog and digital signals for the tmuxout and tmux2out pins. these pins are multiplexed with the seg47 and seg46 function. in order to function as test pins, lcd_map[46] and lcd_map[47] must be 0. see table 11 . the tmuxout and tmux2out pins may be used for diagnostics purposes during the product development cycle or in the production test. the rtc 1-second output may be used to calibrate the crystal oscillator. the rtc 4-second output provides higher precision for rtc cali - bration. rtclk may also be used to calibrate the rtc. downloaded from: http:///
maxim integrated 39 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com tmux[5:0] signal name description 1 rtclk 32.768 khz clock waveform 9 wd_rst indicates when the mpu has reset the watchdog timer. can be monitored to determine spare time in the watchdog timer. a ckmpu mpu clock d v3aok bit indicates that the v3p3a pin voltage is 3.0 v. the v3p3a and v3p3sys pins are expected to be tied together at the pcb level. the 71m6543 monitors the v3p3a pin voltage only. e v3ok bit indicates that the v3p3a pin voltage is 2.8 v. the v3p3a and v3p3sys pins are expected to be tied together at the pcb level. the 71m654 monitors the v3p3a pin voltage only. 1b mux_sync internal multiplexer frame sync signal. 1c ce_busy interrupt 1d ce_xfer interrupt 1f rtm output from ce note: all tmux[5:0] values that are not shown are reserved. tmux2[4:0] signal name description 0 wd_ovf indicates when the watchdog timer has expired (overlowed). 1 pulse_1s one-second pulse with 25% duty cycle. this signal can be used to measure the deviation of the rtc from an ideal 1-second interval. multiple cycles should be averaged together to ilter out jitter. 2 pulse_4s four-second pulse with 25% duty cycle. this signal can be used to measure the deviation of the rtc from an ideal 4-second interval. multiple cycles should be averaged together to ilter out jitter. this pulse provides a more precise measurement than the 1-second pulse. 3 rtclk 32.768 khz clock waveform 8 spare[1] bit C i/o ram 0x2704[1] copies the value of the bit stored in 0x2704[1]. for general purpose use. 9 spare[2] bit C i/o ram 0x2704[2] copies the value of the bit stored in 0x2704[2]. for general purpose use. a wake indicates when a wake event has occurred. b mux_sync internal multiplexer frame sync signal. c mck e gndd digital gnd. use this signal to make the tmux2out pin static. table 11. test ports downloaded from: http:///
maxim integrated 40 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com functional description theory of operation the energy delivered by a power source into a load can be expressed as: t 0 e v(t)i(t)dt = assuming phase angles are constant, the following for - mulae apply: ? p = real energy [wh] = v x a x cos () x t ? q = reactive energy [varh] = v x a x sin () x t ? s = apparent energy [vah] = 22 pq + for a practical meter, not only voltage and current ampli - tudes, but also phase angles and harmonic content may change constantly. thus, simple rms measurements are inherently inaccurate. the 71m654xt, however, functions by emulating the integral operation above by processing current and voltage samples at a constant rate. as long as the adc resolution is high enough and the sample fre - quency is beyond the harmonic range of interest, the cur - rent and voltage samples, multiplied by the sample period yield an accurate value for the instantaneous energy. summing the instantaneous energy quantities over time provides accurate results for accumulated energy. the application of 240v ac and 100a results in an accu - mulation of 480ws (= 0.133 wh) over the 20ms period, as indicated by the accumulated power curve. the described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. battery modes the 71m654xt can operate in one of four power modes: mission (msn), brownout (brn), sleep (slp), or lcd- only (lcd) mode. shortly after system power (v v3p3sys ) is applied, the part is in mission mode. msn mode means that the part is operating with system power and that the internal pll is stable. this mode is the normal operating mode where the part is capable of measuring energy. when system power is not available, the 71m654xt is in one of three battery modes: brn, slp or lcd. an internal comparator monitors the voltage at the v v3p3a pin (note that v v3p3sys and v v3p3a are typically connected together at the pcb level). when the v v3p3a dc voltage drops below 2.8 vdc, the comparator resets an internal power status bit called v3ok. as soon as system power is removed and v3ok = 0, the 71m654xt switches to battery power (v bat pin), notifies the mpu by issuing an interrupt and updates the vstat[2:0] register. the mpu continues to execute code when the system transitions from msn to brn mode. depending on the mpu code, the mpu can choose to stay in brn mode, or transition to lcd or to slp mode. brn mode is similar to msn mode except that resources powered by v v3p3a power, such as the adc are inaccurate. in brn mode the ce continues to run and should be turned off to conserve v bat power. also, the pll continues to function at the same frequency as in msn mode and its frequency should be reduced to save power. tmux[5:0] signal name description 1 rtclk 32.768 khz clock waveform 12 int0 C dig i/o interrupts 13 int1 C dig i/o 14 int2 C ce_pulse 15 int3 C ce_busy 16 int4 - vstat 17 int5 C eeprom/spi 18 int6 C xfer, rtc 1f rtm_ck (lash) note: all tmux2[4:0] values which are not shown are reserved. table 11. test ports (continued) downloaded from: http:///
maxim integrated 41 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 8. waveforms comparing voltage, current, energy per interval, and accumulated energy when system power is restored, the 71m654xt automatically transitions from any of the battery modes (brn, lcd, slp) back to msn mode, switches back to using system power (v v3p3sys , v v3p3a ), issues an interrupt and updates vstat[1:0]. the mpu software should restore msn mode operation by issuing a soft reset to restore system settings to values appropriate for msn mode. transitions from both lcd and slp mode to brn mode can be initiated by the following events: 1) wake-up timer timeout. 2) pushbutton (pb) is activated. 3) a rising edge on segdio4, segdio52, or segdio55. 4) activity on the rx or opt_rx pins. brownout mode in brn mode, most nonmetering digital functions are active including ice, uart, eeprom, lcd and rtc. in brn mode, the pll continues to function at the same fre - quency as msn mode. it is up to the mpu to reduce the pll frequency or the mpu frequency in order to minimize power consumption. from brn mode, the mpu can choose to enter lcd or slp modes. when system power is re stored while the 71m654xt is in brn mode, the part automatically transi - tions to msn mode.lcd only mode lcd mode may be commanded by the mpu at any time by setting the lcd_only control bit. however, it is rec - ommended that the lcd_only control bit be set by the mpu only after the 71m654xt has entered brn mode. for example, if the 71m654xt is in msn mode when lcd_only is set, the duration of lcd mode is very brief and the 71m654xt immediately wakes. in lcd mode, v v3p3d is disabled, thus removing all current leakage from the v bat pin. before asserting lcd_only mode, it is recommended that the mpu minimize pll current by reducing the output frequency of the pll to 6.2mhz (i.e., write pll_fast = 0). -500 -400 -300 -200 -100 0 100 200 300 400 500 05 10 15 20 time (ms) v(v), i(a), p(ws) vol ta ge (v) current (a) energy per inter va l (ws) accumulated energy (ws) downloaded from: http:///
maxim integrated 42 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com in lcd mode, the data contained in the lcd_seg reg - isters is displayed using the segment driver pins. up to two lcd segments connected to the pins segdio22 and segdio23 can be made to blink without the involvement of the mpu, which is disabled in lcd mode. to minimize battery power consumption, only segments that are used should be enabled. after the transition from lcd mode to msn or brn mode, the pc (program counter) is at 0x0000, the xram is in an undefined state, and configuration i/o ram bits are reset (see table 12 ) for i/o ram state upon wake). the data stored in nonvolatile i/o ram locations is preserved in lcd mode (the shaded locations in table 12 are non - volatile). sleep modewhen the v v3p3sys pin voltage drops below 2.8 vdc, the 71m654xt enters brn mode and the v v3p3d pin obtains power from the v bat pin instead of the v v3p3sys pin. once in brn mode, the mpu may invoke slp mode by setting the sleep bit. the purpose of slp mode is to consume the least amount power while still maintaining the real time clock, temperature compensation of the rtc, and the nonvolatile portions of the i/o ram. in slp mode, the v v3p3d pin is disconnected, removing all sources of current leakage from the v bat pin. the nonvolatile i/o ram locations and the slp mode functions, such as the temperature sensor, oscillator, rtc, and the rtc temperature compensation are powered by the v bat_rtc pin. slp mode can be exited only by a system power-up event or one of the wake methods. if the sleep bit is asserted when v v3p3sys pin power is present (i.e., while in msn mode), the 71m654xt enters slp mode, resetting the internal wake signal, at which point the 71m654xt begins the standard wake from sleep procedures. when power is restored to the v v3p3sys pin, the 71m654xt transitions from slp mode to msn mode and the mpu pc (program counter) is initialized to 0x0000. at this point, the xram is in an undefined state, but nonvolatile i/o ram locations are preserved. figure 10. typical current-sense circuit using current transformer in a single-ended configuration figure 9. typical voltage sense circuit using resistive divider r in v in vav3p3 a r out v out i out iapv3p3 a ct 1:n i in r burden noise filter downloaded from: http:///
maxim integrated 43 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 11. typical current-sense circuit using current transformer in a differential configuration figure 12. typical current-sense circuit using shunt in a differential configuration i out iapian v3p3a ct 1:n i in v out r burden bias network and noise fi lt er i in iapian v3p3a v out r shunt bias network and noise fi lt er downloaded from: http:///
maxim integrated 44 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 13. 71m6543ft/ht/gt/ght typical operating circuit using locally connected sensors mpu rtc timers iadc2iadc4 iadc5 va dc9 (vb) iadc6iadc7 va dc10 (vc) iadc0iadc1 xin xout rxtx txrx com0...5 v3p3a v3 p3 sy s *i n = op ti onal ne ut ra l curren t vbat vbat_rtc seg gnda gndd seg/dio dio ice neutral current transformers load a b c pulses, dio ir amr power fault compara to r modula to r serial ports oscilla to r/pll mux and adc lcd driver dio, pulses compute engine flash memory ram 32 khz regula to r power supply 71m6543ft 71m6543ht 71m6543gt 71m6543ght temperature sensor vref batte ry rt c batte ry pwr mode control wake-up i 2 c or wire eeprom iadc3va dc8 (va) iaib ic in* v3p3d batte ry monitor spi interface host lcd display resistor dividers neutral note: this system is referenced to neutral downloaded from: http:///
maxim integrated 45 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 14. 71m6543ft/ht/gt/ght typical operating circuit using remote neutral current sensor mpu rtc timers xin xout rxtx txrx v3p3a v3p3sys vbat vbat_rtc gnda gndd ice ir amr power fault compara to r modula to r serial ports oscilla to r/pll lcd driver dio, pulses compute engine flash memory ram 32 khz regula to r power supply 71m6543ft 71m6543ht 71m6543gt 71m6543ght temperature sensor vref batte ry rt c batte ry pwr mode control wake-up batte ry monitor spi interface host iadc0va dc9 (vb) iadc4iadc5 va dc8 (va) iadc2iadc3 neutral shunt current sensors load c b a mux and adc iadc1va dc10 (vc) iadc6iadc7 in*ic ib ia resistor dividers note: this system is referenced to neutral 3x 71m6xx3 pulse transformers neutral 71m6xx3 71m6xx3 71m6xx3 *i n = ne ut ra l curren t com0...5 seg seg/dio dio pulses, dio i 2 c or wire eeprom v3p3d lcd display downloaded from: http:///
maxim integrated 46 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com applications information connecting 5v devices all digital input pins of the 71m654xt are compatible with external 5v devices. i/o pins configured as inputs do not require current-limiting resistors when they are connected to external 5v devices. direct connection of sensors the 71m654xt supports direct connection of current transformer and shunt-fed sensors. using the 71m6543ft/ht/gt/ght with local sensors the 71m6543ft/ht/gt/ght can be configured to oper - ate with locally connected current sensors. all current inputs are connected to a current transformer (ct) and are therefore isolated. this configuration implements a poly - phase measurement with tamper-detection using one current sensor to measure the neutral current. for best performance, all current sensor inputs are configured for differential mode. using the 71m6543ft/ht/gt/ght with remote sensors the 71m6543ft/ht/gt/ght can be configured to oper - ate with 71m6x03 remote sensor interfaces and current shunts. this configuration implements a polyphase mea - surement with tamper-detection. for best performance, the iadc0-iadc1 current sensor input is configured for differential mode (diffa_e = 1). the outputs of the 71m6x03 isolated sensor interface are routed through a pulse transformer, which is connected to the current input pins (iadc2-iadc7). the current input pins (iadc2- iadc7) must be configured for remote sensor communi - cation (i.e., rmt_e =1). metrology temperature compensation since the v ref bandgap amplifier is chopper-stabilized the dc offset voltage (the most significant long-term drift mechanism in bandgap voltage references) is automatically removed by the chopper circuit. both the 71m654xt and the 71m6x03 feature chopper circuits for their respective v ref voltage reference. v ref is trimmed to a target value of 1.195v during the device manufacturing process and the result of the trim stored in nonvolatile fuses. for the 71m654xt device (q0.5% energy accuracy), the trimt[7:0] value can be read by the mpu during initialization in order to calculate parabolic temperature compensation coefficients suitable for each individual 71m654xt device. the resulting temperature coefficient for v ref in the 71m654xt is 40 ppm/c. by using the trim information in the trimt register and the sensed temperature, a gain adjustment for the sensor can be computed. see the 71m6543ft/ht/gt/ght users guide for more information about compensating sensors for temperature variations.connecting i 2 c eeproms i 2 c eeproms or other i 2 c compatible devices should be connected to the dio pins segdio2 and segdio3. pullup resistors of roughly 10k? to v v3p3d (to ensure operation in brn mode) should be used for both sdck and sdata signals. the dio_eex[1:0] field in i/o ram must be set to 01 in order to convert the dio pins segdio2 and segdio3 to i 2 c pins sdck and sdata. connecting three-wire eeproms microwire eeproms and other compatible devices should be connected to the dio pins segdio2/sdck and segdio3/sdata. uart0 the uart0 rx pin should be pulled down by a 10k? resistor and additionally protected by a 100pf ceramic capacitor. optical interface the opt_tx and opt_rx pins can be used for a regular serial interface (by connecting a rs_232 transceiver for example), or they can be used to directly operate optical components (for example, an infrared diode and pho - totransistor implementing a flag interface). figure 16 shows the basic connections for uart1. the opt_tx pin becomes active when the i/o ram control field opt_ txe (i/o ram 0x2456[3:2]) is set to 00. the polarity of the opt_tx and opt_rx pins can be inverted with the configuration bits, opt_txinv and opt_rxinv, re spectively. the opt_tx output may be modulated at 38khz when system power is present. modulation is not available in brn mode. the opt_txmod bit enables modulation. the duty cycle is controlled by opt_fdc[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. a 6.25% duty cycle means opt_tx is low for 6.25% of the period. the opt_rx pin uses digital signal thresholds. it may need an analog filter when receiving modulated optical signals. with modulation, an optical emitter can be operated at higher current than nominal, enabling it to increase the distance along the optical path. downloaded from: http:///
maxim integrated 47 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 16. typical uart operating circuit figure 18. optical interface typical operating circuit figure 17. typical reset circuits if operation in brn mode is desired, the external components should be connected to v v3p3d . however, it is recommended to limit the current to a few ma.reset even though a functional meter does not necessarily need a reset switch, it is useful to have a reset push- button for prototyping. the reset signal may be sourced from v v3p3sys (functional in msn mode only), v v3p3d (msn and brn modes), or v bat (all modes, if a battery is present), or from a combination of these sources, depending on the application. reset causes the cpu to restart and returns all io ram values to their default values. for a production meter, the reset pin should be protect - ed by the external components. r1 should be in the range of 100? and mounted as closely as possible to the ic. emulator port pins even when the emulator is not used, small shunt capaci - tors to ground (22pf) should be used for protection from emi. production boards should have the ice_e pin con - nected to ground. mpu firmware library all application-specific mpu functions are featured in the demonstration c source code supplied by maxim integrated. the code is available as part of the demonstration kit for the 71m6543ft/gt/ght. the demonstration kits come with pre programmed with demo firmware and mounted on a functional sample meter demo board. the demo boards allow for quick and efficient evaluation of the ic without hav - ing to write firmware or having to supply an in-circuit emulator (ice). contact maxim integrated for information on price and availability of demonstration boards. figure 15. typical i 2 c operating circuit figure 19. typical emulator connections 10k rx 71m654xt rx 100pf tx tx 10k r1 r2 71m654xt opt_rx 100pf v3p3sys v3p3sys phototransistor led opt_tx r1 10k r2 1k 71m654xt v3p3d vbat/ v3p3d reset switch 0.1f resetgndd r1 100 resetgndd 10k v3p3d sdck eeprom 71m654xt segdio2/sdck 10k sdata segdio3/sdata 62 71m654xt e_rst 22pf 22pf 22pf 62 e_rxt 62 e_tclk ice_e v3p3d lcd segments (optional) downloaded from: http:///
maxim integrated 48 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 12. i/o ram locations in numerical order name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce6 2000 equ[2:0] u chop_e[1:0] rtm_e ce_e ce5 2001 u u u sum_samps[12:8] ce4 2002 sum_samps[7:0] ce3 2003 u ce_lctn[6:0] for 71m6543gt/ght, ce_lctn[5:0] for 71m6543ft/ht ce2 2004 pls_maxwidth[7:0] ce1 2005 pls_interval[7:0] ce0 2006 diff6_e diff4_e diff2_e diff0_e rfly_dis fir_len[1:0] pls_inv rce0 2007 chopr[1:0] rmt6_e rmt4_e rmt2_e r r r rtmux 2008 u tmuxrb[2:0] u tmuxra[2:0] reserved 2009 u u r u u u u u mux5 200a mux_div[3:0] mux10_sel mux4 200b mux9_sel mux8_sel mux3 200c mux7_sel mux6_sel mux2 200d mux5_sel mux4_sel mux1 200e mux3_sel mux2_sel mux0 200f mux1_sel mux0_sel temp 2010 temp_bsel temp_pwr osc_comp temp_bat u temp_per[2:0] lcd0 2011 lcd_e lcd_mode[2:0] lcd_allcom lcd_y lcd_clk[1:0] lcd1 2012 lcd_vmode[1:0] lcd_blnkmap23[5:0] lcd2 2013 lcd_bat r lcd_blnkmap22[5:0] lcd_map6 2014 lcd_map[55:48] lcd_map5 2015 lcd_map[47:40] lcd_map4 2016 lcd_map[39:32] lcd_map3 2017 lcd_map[31:24] lcd_map2 2018 lcd_map[23:16] lcd_map1 2019 lcd_map[15:8] lcd_map0 201a lcd_map[7:0] dio_r5 201b u u u u u dio_rpb[2:0] dio_r4 201c u dio_r11[2:0] u dio_r10[2:0] dio_r3 201d u dio_r9[2:0] u dio_r8[2:0] dio_r2 201e u dio_r7[2:0] u dio_r6[2:0] dio_r1 201f u dio_r5[2:0] u dio_r4[2:0] dio_r0 2020 u dio_r3[2:0] u dio_r2[2:0] dio0 2021 dio_eex[1:0] u u opt_txe[1:0] opt_txmod opt_txinv dio1 2022 dio_pw dio_pv opt_fdc[1:0] u opt_rxdis opt_rxinv opt_bb dio2 2023 dio_px dio_py u u u u u u int1_e 2024 ex_eex ex_xpulse ex_ypulse ex_rtct ex_tctemp ex_rtc1m ex_rtc1s ex_xfer int2_e 2025 ex_spi ex_wpulse ex_vpulse wake_e 2026 u ew_temp u ew_rx ew_pb ew_dio4 ew_dio52 ? ew_dio55 sfmm 2080 sfmm[7:0] (via spi slave port only) sfms 2081 sfms[7:0] (via spi slave port only) ce and adc mux5 2100 mux_div[3:0] mux10_sel[3:0] mux4 2101 mux9_sel[3:0] mux8_sel[3:0] mux3 2102 mux7_sel[3:0] mux6_sel[3:0] mux2 2103 mux5_sel[3:0] mux4_sel[3:0] mux1 2104 mux3_sel[3:0] mux2_sel[3:0] mux0 2105 mux1_sel[3:0] mux0_sel[3:0] ce6 2106 equ[2:0] u chop_e[1:0] rtm_e ce_e ce5 2107 u u u sum_samps[12:8] ce4 2108 sum_samps[7:0] ce3 2109 u ce_lctn[6:0] for 71m6543gt/ght, ce_lctn[5:0] for 71m6543ft/ht downloaded from: http:///
maxim integrated 49 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 12. i/o ram locations in numerical order (continued) name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ce2 210a pls_maxwidth[7:0] ce1 210b pls_interval[7:0] ce0 210c r r diffb_e diffa_e rfly_dis fir_len[1:0] pls_inv ce0 rtm0 210d u u u u u u rtm0[9:8] rtm0 210e rtm0[7:0] rtm1 210f rtm1[7:0] rtm2 2110 rtm2[7:0] rtm3 2111 rtm3[7:0] fir_ext 2112 u u u u slot_ext[3:0] clock generation ckgn 2200 out_sq[1:0] adc_div pll_fast reset mpu_div[2:0] v ref trim fuses trimt 2309 trimt[7:0] lcd/dio lcd0 2400 lcd_e lcd_mode[2:0] lcd_allcom lcd_y lcd_clk[1:0] lcd1 2401 lcd_vmode[1:0] lcd_blnkmap23[5:0] lcd2 2402 lcd_bat r lcd_blnkmap22[5:0] lcd_map6 2405 lcd_map[55:48] lcd_map5 2406 lcd_map[47:40] lcd_map4 2407 lcd_map[39:32] lcd_map3 2408 lcd_map[31:24] lcd_map2 2409 lcd_map[23:16] lcd_map1 240a lcd_map[15:8] lcd_map0 240b lcd_map[7:0] lcd4 240c u u u u u lcd_rst lcd_blank lcd_on lcd_dac 240d u u u lcd_dac[4:0] segdio0 2410 u u lcd_seg0[5:0] segdio1 2411 u u lcd_seg1[5:0] segdio2 2412 u u lcd_seg2[5:0] segdio3 2413 u u lcd_seg3[5:0] segdio4 2414 u u lcd_seg4[5:0] segdio5 2415 u u lcd_seg5[5:0] segdio6 2416 u u lcd_seg6[5:0] segdio7 2417 u u lcd_seg7[5:0] segdio8 2418 u u lcd_seg8[5:0] segdio9 2419 u u lcd_seg9[5:0] segdio10 241a u u lcd_seg10[5:0] segdio11 241b u u lcd_seg11[5:0] segdio12 241c u u lcd_seg12[5:0] segdio13 241d u u lcd_seg13[5:0] segdio14 241e u u lcd_seg14[5:0] segdio15 241f u u lcd_seg15[5:0] segdio16 2420 u u lcd_seg16[5:0] segdio17 2421 u u lcd_seg17[5:0] segdio18 2422 u u lcd_seg18[5:0] segdio19 2423 u u lcd_seg19[5:0] segdio20 2424 u u lcd_seg20[5:0] segdio21 2425 u u lcd_seg21[5:0] segdio22 2426 u u lcd_seg22[5:0] segdio23 2427 u u lcd_seg23[5:0] segdio24 2428 u u lcd_seg24[5:0] segdio25 2429 u u lcd_seg25[5:0] downloaded from: http:///
maxim integrated 50 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 12. i/o ram locations in numerical order (continued) name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 segdio26 242a u u lcd_seg26[5:0] segdio27 242b u u lcd_seg27[5:0] segdio28 242c u u lcd_seg28[5:0] segdio29 242d u u lcd_seg29[5:0] segdio30 242e u u lcd_seg30[5:0] segdio31 242f u u lcd_seg31[5:0] segdio32 2430 u u lcd_seg32[5:0] segdio33 2431 u u lcd_seg33[5:0] segdio34 2432 u u lcd_seg34[5:0] segdio35 2433 u u lcd_seg35[5:0] segdio36 2434 u u lcd_seg36[5:0] segdio37 2435 u u lcd_seg37[5:0] segdio38 2436 u u lcd_seg38[5:0] segdio39 2437 u u lcd_seg39[5:0] segdio40 2438 u u lcd_seg40[5:0] segdio41 2439 u u lcd_seg41[5:0] segdio42 243a u u lcd_seg42[5:0] segdio43 243b u u lcd_seg43[5:0] segdio44 243c u u lcd_seg44[5:0] segdio45 243d u u lcd_seg45[5:0] segdio46 243e u u lcd_seg46[5:0] segdio47 243f u u lcd_seg47[5:0] segdio48 2440 u u lcd_seg48[5:0] segdio49 2441 u u lcd_seg49[5:0] segdio50 2442 u u lcd_seg50[5:0] segdio51 2443 u u lcd_seg51[5:0] segdio52 2444 u u lcd_seg52[5:0] segdio53 2445 u u lcd_seg53[5:0] segdio54 2446 u u lcd_seg54[5:0] segdio55 2447 u u lcd_seg55[5:0] dio_r5 2450 u u u u u dio_rpb[2:0] dio_r4 2451 u dio_r11[2:0] u dio_r10[2:0] dio_r3 2452 u dio_r9[2:0] u dio_r8[2:0] dio_r2 2453 u dio_r7[2:0] u dio_r6[2:0] dio_r1 2454 u dio_r5[2:0] u dio_r4[2:0] dio_r0 2455 u dio_r3[2:0] u dio_r2[2:0] dio0 2456 dio_eex[1:0] u umux_sel opt_txe[1:0] opt_txmod opt_txinv dio1 2457 dio_pw dio_pv opt_fdc[1:0] u opt_rxdis opt_rxinv opt_txinv dio2 2458 dio_px dio_py u out_sqe u u u u nonvolatile bits tmux 2502 u u tmux[5:0] tmux2 2503 u u u tmux2[4:0] tc_a1 2508 u u u u u u tc_a[9:8] tc_a2 2509 tc_a[7:0] tc_b1 250a u u u u tc_b[11:8] tc_b2 250b tc_b[7:0] pqmask 2511 u u u u u pqmask[2:0] tsel 2518 u u u temp_sele temp_sel[3:0] tsbase1 2519 u u u u u sbase[10:8] tsbase2 251a sbase[7:0] tsmax 251b u smax[6:0] tsmin 251c u smin[6:0] downloaded from: http:///
maxim integrated 51 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 12. i/o ram locations in numerical order (continued) name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tsfilt 251d u u u u sfilt[3:0] 71m6x03 remote interface remote2 2602 rmt_rd[15:8] remote1 2603 rmt_rd[7:0] rbits int1_e 2700 ex_eex ex_xpulse ex_ypulse ex_rtct ex_tctemp ex_rtc1m ex_rtc1s ex_xfer int2_e 2701 ex_spi ex_wpulse ex_vpulse u u u u u secure 2702 flsh_unlock[3:0] r flsh_rde flsh_wre r analog0 2704 vref_cal vref_dis pre_e adc_e bcurr spare[2:0] intbits 2707 u int6 int5 int4 int3 int2 int1 int0 flag0 sfr e8 ie_eex ie_xpulse ie_ypulse ie_rtct ie_tctemp ie_rtc1m ie_rtc1s ie_xfer flag1 sfr f8 ie_spi ie_wpulse ie_vpulse u u u u pb_state stat sfr f9 u u u pll_ok u vstat[2:0] remote0 sfr fc u perr_rd perr_wr rcmd[4:0] spi1 sfr fd spi_cmd[7:0] spi0 2708 spi_stat[7:0] rce0 2709 chopr[1:0] r r rmt_e r r r rtmux 270a u r r r u tmuxra[2:0] info_pg 270b u u u u u u u info_pg dio3 270c u u port_e spi_e spi_safe u u u tnm1 2710 u temp_nmax[14:8] tnm2 2711 temp_nmax[7:0] tm1 2712 u u u u temp_m[11:8] tm2 2713 temp_m[7:0] tnb1 2714 temp_nbat[15:8] tnb2 2715 temp_nbat[7:0] nv ram and rtc nvramxx 2800 nvram[0] to nvram[7f] - 128 bytes, direct access, 0x2800 to 0x287f wake 2880 wake_tmr[7:0] stemp1 2881 stemp[15:8] stemp0 2882 stemp[7:0] bsense 2885 bsense[7:0] pq2 2886 u u u pq[20:16] pq1 2887 pq[15:8] pq0 2888 pq[7:0] rtc0 2890 rtc_wr rtc_rd u rtc_fail u u u u rtc2 2892 rtc_sbsc[7:0] rtc3 2893 u u rtc_sec[5:0] rtc4 2894 u u rtc_min[5:0] rtc5 2895 u u u rtc_hr[4:0] rtc6 2896 u u u u u rtc_day[2:0] rtc7 2897 u u u rtc_date[4:0] rtc8 2898 u u u u rtc_mo[3:0] rtc9 2899 rtc_yr[7:0] rtc11 289c u u u u tc_c[11:8] rtc12 289d tc_c[7:0] rtc13 289e u u rtc_tmin[5:0] rtc14 289f u u u rtc_thr[4:0] temp 28a0 temp_bsel temp_pwr osc_comp temp_bat tbyte_busy temp_per[2:0] wf1 28b0 wf_cstart wf_rst wf_rstbit wf_ovf wf_erst wf_badvdd u u wf2 28b1 u wf_temp wf_tmr wf_rx wf_pb wf_dio4 wf_dio52 wf_dio55 misc 28b2 sleep lcd_only wake_arm u u u u u downloaded from: http:///
maxim integrated 52 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 12. i/o ram locations in numerical order (continued) name addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wake_e 28b3 u ew_temp u ew_rx ew_pb ew_dio4 ew_dio52 ? ew_dio55 wdrst 28b4 wd_rst temp_start u u u u u u mpu ports p3 sfr b0 dio_dir[15:12] dio[15:12] p2 sfr a0 dio_dir[11:8] dio[11:8] p1 sfr 90 dio_dir[7:4] dio[7:4] p0 sfr 80 dio_dir[3:0] dio[3:0] flash flash_ erase sfr 94 flsh_erase[7:0] flsh_ctl sfr b2 preboot secure u u flsh_pend flsh_pstwr flsh_meen flsh_pwe flsh_bank sfr b6 u u u u u u flsh_bank[1:0] flsh_ pgadr sfr b7 flsh_pgadr[6:0] u i 2 c eedata sfr 9e eedata[7:0] eectrl sfr 9f eectrl[7:0] downloaded from: http:///
maxim integrated 53 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order name location rstwk dir description adc_e 2704[4] 0 0 r/w enables adc and v ref . when disabled, reduces bias current. adc_div 2200[5] 0 0 r/w adc_div controls the rate of the adc and fir clocks. the adc_div setting determines whether mck is divided by 4 or 8: 0 = mck/4 1 = mck/8 the resulting adc and fir clock is as shown below. pll_fast = 0 pll_fast = 1 mck 6.291456mhz 19.660800mhz adc_div = 0 1.572864mhz 4.9152mhz adc_div = 1 0.786432mhz 2.4576mhz bcurr 2704[3] 0 0 r/w connects a 100a load to the battery selected by temp_bsel. bsense[7:0] 2885[7:0] C C r the result of the battery measurement. ce_e 2106[0] 0 0 r/w ce enable. ce_lctn[6:0] ce_lctn[5:0] 2109[6:0]2109[5:0] 31 31 r/w ce program location. the starting address for the ce program is 1024 x ce_lctn. ce_lctn[6:0], 2109[6:0] for 71m6543gt/ght; ce_lctn[5:0], 2109[5:0] for 71m6543ht/ght. chip_id[15:0] 2300[7:0]2301[7:0] 00 00 rr these bytes contain the chip identiication.chip_id[15:0]: 71m6543ft (0810h) 71m6543ht (11ach) 71m6543gt (2019h) 71m6543ght (2021h) chop_e[1:0] 2106[3:2] 0 0 r/w chop enable for the reference bandgap circuit. the value of chop changes on the rising edge of muxsync according to the value in chop_e (note: chop_e = 11 is the preferred mode for low-noise applications): 00 = toggle 1 01 = positive 10 = reversed 11 = toggle 1 except at the mux sync edge at the end of an accumulation interval. note: chop_e = 11 is the preferred mode for low-noise applications. chopr[1:0] 2709[7:6] 00 00 r/w the chop settings for the remote sensor. 00 = auto chop. change every mux frame. 01 = positive 10 = negative 11 = auto chop. same as 00. diff0_e 210c[4] 0 0 r/w enables iadc0-iadc1 differential coniguration. diff2_e 210c[5] 0 0 r/w enables iadc2-iadc3 differential coniguration. diff4_e 210c[6] 0 0 r/w enables iadc4-iadc5 differential coniguration. diff6_e 210c[7] 0 0 r/w enables iadc6-iadc7 differential coniguration. dio_r2[2:0]dio_r3[2:0] dio_r4[2:0] dio_r5[2:0] dio_r6[2:0] dio_r7[2:0] dio_r8[2:0] dio_r9[2:0] dio_r10[2:0] dio_r11[2:0] dio_rpb[2:0] 2455[2:0]2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] 00 0 0 0 0 0 0 0 0 0 - r/w connects pb and dedicated i/o pins dio2 through dio11 to internal resources. if more than one input is connected to the same resource, the multiple column below speciies how they are combined. dio_rx resource multiple 0 none C 1 reserved or 2 t0 (timer0 clock or gate) or 3 t1 (timer1 clock or gate) or 4 io interrupt (int0) or 5 io interrupt (int1) or dio_dir[15:12] dio_dir[11:8] dio_dir[7:4] dio_dir[3:0] sfr b0[7:4] sfr a0[7:4] sfr 90[7:4]sfr 80[7:4] f f r/w programs the direction of the irst 16 dio pins. 1 indicates output. ignored if the pin is not conigured as i/o. see dio_pv and dio_pw for special option for the segdio0 and segdio1 outputs. see dio_eex for special option for segdio2 and segdio3. note that the direction of dio pins above 15 is set by segdiox[1]. see port_e to avoid power-up spikes. dio[15:12] dio[11:8] dio[7:4] dio[3:0] sfr b0[3:0] sfr a0[3:0] sfr 90[3:0] sfr 80[3:0] f f r/w the value on the irst 16 dio pins. pins conigured as lcd reads zero. when written, changes data on pins conigured as outputs. pins conigured as lcd or input ignore writes. note that the data for dio pins above 15 is set by segdiox[0]. downloaded from: http:///
maxim integrated 54 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description dio_eex[1:0] 2456[7:6] 0 - r/w when set, converts pins segdio3/segdio2 to interface with external eeprom. segdio2 becomes sdck and segdio3 becomes bidirectional sdata, but only if lcd_map[2] and lcd_map[3] are cleared. dio_eex[1:0] function 00 disable eeprom interface 01 2-wire eeprom interface 10 3-wire eeprom interface 11 3-wire eeprom interface with separate do (dio3) and di (dio8) pins. dio_pv 2457[6] 0 C r/w causes varpulse to be output on pin segdio1, if lcd_map[1] = 0. dio_pw 2457[7] 0 C r/w causes wpulse to be output on pin segdio0, if lcd_map[0] = 0. dio_px 2458[7] 0 C r/w causes xpulse to be output on pin segdio6, if lcd_map[6] = 0. dio_py 2458[6] 0 C r/w causes ypulse to be output on pin segdio7, if lcd_map[7] = 0. eedata[7:0] sfr 9e 0 0 r/w serial eeprom interface data. eectrl[7:0] sfr 9f 0 0 r/w serial eeprom interface control. status bit name read/ write reset state polarity description 7 error r 0 positive 1 when an illegal command is received. 6 busy r 0 positive 1 when serial data bus is busy. 5 rx_ack r 1 positive 1 indicates that the eeprom sent an ack bit. equ[2:0] 2106[7:5] 0 0 r/w speciies the power equation. equ[2:0] description element 0 element 1 element 2 recommended mux sequence 3 2 element 4w 3 f delta va(ia-ib)/2 0 vc x ic ia va ib vb ic vc 4 2 element 4w 3 f wye va(ia-ib)/2 vb(ic-ib)/2 0 ia va ib vb ic vc 5 2 element 4w 3 f wye va x ia vb x ib vc x ic ia va ib vb ic vc note: the available ce codes implement only equation 5. contact your maxim representative to obtain ce codes for equation 3 or 4. ex_xfer ex_rtc1s ex_rtc1m ex_tctemp ex_rtct ex_spi ex_eex ex_xpulse ex_ypulse ex_wpulse ex_vpulse 2700[0]2700[1] 2700[2] 2700[3] 2700[4] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] 0 0 r/w interrupt enable bits. these bits enable the xfer_busy, the rtc_1sec, etc. the bits are set by hardware and cannot be set by writing a 1. the bits are reset by writing 0. note that if one of these interrupts is to enabled, its corresponding 8051 ex enable bit must also be set. ew_dio4 28b3[2] 0 C r/w connects segdio4 to the wake logic and permits segdio4 rising to wake the part. this bit has no effect unless dio4 is conigured as a digital input. ew_dio52 28b3[1] 0 C r/w connects segdio52 to the wake logic and permits segdio52 rising to wake the part. this bit has no effect unless segdio52 is conigured as a digital input. ew_dio55 28b3[0] 0 C r/w connects segdio55 to the wake logic and permits segdio55 rising to wake the part. this bit has no effect unless segdio55 is conigured as a digital input. ew_pb 28b3[3] 0 C r/w connects pb to the wake logic and permits pb rising to wake the part. pb is always conigured as an i nput. ew_rx 28b3[4] 0 C r/w connects rx to the wake logic and permits rx rising to wake the part. see the wake description on page 84 for de-bounce issues. ew_temp 28b3[5] 0 C r/w connects the temperature range check hardware to the wake logic and permits the range check hardware to wake the part. downloaded from: http:///
maxim integrated 55 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description fir_len[1:0] 210c[2:1] 0 0 r/w determines the number of adc cycles in the adc decimation fir ilter. pll_fast = 1: fir_len[1:0] adc cycles 00 141 01 288 10 384 pll_fast = 0: fir_len[1:0] adc cycles 00 135 01 276 10 not allowed the adc lsb size and full-scale values depend on the fir_len[1:0] setting. flsh_bank sfr b6[1:0] 01 01 r/w flash bank selection flsh_bank[1:0] address range for lower bank (0x0000C0x7fff) address range for upper bank (0x8000C0x7fff) 00 0x0000C0x7fff 0x0000C0x7fff 01 0x0000C0x7fff 0x8000C0x7fff 10 0x0000C0x7fff 0x10000C0x17ffff 11 0x0000C0x7fff 0x18000C0x1ffff flsh_erase[7:0] sfr 94[7:0] 0 0 w flash erase initiateflsh_erase is used to initiate either the flash mass erase cycle or the flash page erase cycle. spec iic patterns are expected for flsh_erase in order to initiate the appropriate erase cycle. (default = 0x00). 0x55 = initiate flash page erase cycle. must be proceeded by a write to flsh_pgadr[6:0] (sfr 0xb7[7:1]). 0xaa = initiate flash mass erase cycle. must be proceeded by a write to flsh_meen and the ice port must be enabled. any other pattern written to flsh_erase has no effect. flsh_meen sfr b2[1] 0 0 w mass erase enable0 = mass erase disabled (default). 1 = mass erase enabled. must be re-written for each new mass erase cycle. flsh_pend sfr b2[3] 0 0 r indicates that a timed lash write is pending. if another lash write is attempted, it is ignored. flsh_pgadr[6:0] sfr b7[7:1] 0 0 w flash page erase address flash page address (page 0 thru 63) that is erased during the page erase cycle. (default = 0x00). must be re-written for each new page erase cycle. flsh_pstwr sfr b2[2] 0 0 r/w enables timed lash writes. when 1, and if ce_e = 1, lash write requests are stored in a one-element deep fifo and are executed when ce_busy falls. flsh_pend can be read to determine the status of the fifo. if flsh_ pstwr = 0 or if ce_e = 0, lash writes are immediate. flsh_pwe sfr b2[0] 0 0 r/w program write enable 0 = movx commands refer to external ram space, normal operation (default). 1 = movx @dptr,a moves a to external program space (flash) @ dptr. this bit is automatically reset after each byte written to lash. writes to this bit are inhibited wh en interrupts are enabled. flsh_rde 2702[2] C C r indicates that the lash may be read by ice or spi slave. flsh_rde = (!secure) flsh_unlock [3:0] 2702[7:4] 0 0 r/w must be a 2 to enable any lash modiication. see the description of flash security for more details . flsh_wre 2702[1] C C r indicates that the lash may be written through ice or spi slave ports. ie_xfer ie_rtc1s ie_rtc1m ie_tctemp ie_rtct ie_spi ie_eex ie_xpulse ie_ypulse ie_wpulse ie_vpulse sfr e8[0]sfr e8[1] sfr e8[2] sfr e8[3] sfr e8[4] sfr f8[7] sfr e8[7]sfr e8[6] sfr e8[5] sfr f8[4]sfr f8[3] 0 0 r/w interrupt lags for external interrupts 2, 5, and 6. these lags monitor the source of the int2, int5, and int6 interrupts (external interrupts to the mpu core). these lags are set by hardware and must be cleared by the sof tware interrupt handler. the iex2 (sfr 0xc0[1]) and iex6 (sfr 0xc0[5]) interrupt lags are automatically cl eared by the mpu core when it vectors to the interrupt handler. iex2 and iex6 must be cleared by writing zero to their corresponding bit positions in sfr 0xc0, while writing ones to the other bit positions that are not being cleared. downloaded from: http:///
maxim integrated 56 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description intbits 2707[6:0] C C r interrupt inputs. the mpu may read these bits to see the input to external interrupts int0, int1, up to int6. these bits do not have any memory and are primarily intended for debug use. lcd_allcom 2400[3] 0 C r/w conigures seg/com bits as com. has no effect on pins whose lcd_map bit is zero. lcd_bat 2402[7] 0 C r/w connects the lcd power supply to v bat in all modes. lcd_blnkmap23 [5:0]lcd_blnkmap22 [5:0] 2401[5:0]2402[5:0] 0 C r/w identiies which segments connected to seg23 and seg22 should blink. 1 means blink. the most signii cant bit corresponds to com5, the least signiicant, to com0. lcd_clk[1:0] 2400[1:0] 0 C r/w sets the lcd clock frequency. note: fw = 32,768hz lcd_clk lcd clock frequency (hz) 00 64 01 128 10 256 11 512 lcd_dac[4:0] 240d[4:0] 0 C r/w the lcd contrast dac. this dac controls the v lcd voltage and has an output range of 2.5v to 5v. the vlcd voltage is v lcd = 2.5 + 2.5 x lcd_dac[4:0]/31 thus, the lsb of the dac is 80.6mv. the maximum dac output voltage is limited by v v3p3sys , v bat , and whether lcd_bste = 1. lcd_e 2400[7] 0 C r/w enables the lcd display. when disabled, vlc2, vlc1, and vlc0 are ground as are the com and seg outputs if their lcd_map bit is 1. lcd_map[55:48]lcd_map[47:40] lcd_map[39:32] lcd_map[31:24] lcd_map[23:16] lcd_map[15:8] lcd_map[7:0] 2405[7:0]2406[7:0] 2407[7:0] 2408[7:0] 2409[7:0] 240a[7:0]240b[7:0] 00 0 0 0 0 0 CC C C C C C r/wr/w r/w r/w r/w r/w r/w enables lcd segment driver mode of combined segdio pins. pins that cannot be conigured as outputs (seg48 through seg50) become inputs with internal pull ups when their lcd_map bit is zero. also, note that seg48 through seg50 are multiplexed with the in-circuit emulator signals. when the ice_e pin is high, the ice interface is enabled, and seg48 through seg50 become e_rxtx, e_tclk and e_rst, respectively. lcd_mode[2:0] 2400[6:4] 0 C r/w selects the lcd bias and multiplex mode. lcd_mode output 000 4 states, ? bias 001 3 states, ? bias 010 2 states, ? bias 011 3 states, ? bias 100 static display 101 5 states, ? bias 110 6 states, ? bias lcd_onlcd_blank 240c[0]240c[1] 00 CC r/wr/w turns on or off all lcd segments without changing lcd data. if both bits are set, the lcd display is turned on. lcd_only 28b2[6] 0 0 w puts the ic to sleep, but with lcd display still active. ignored if system power is present. it awakens when wake timer times out, when certain dio pins are raised, or when system power returns. lcd_rst 240c[2] 0 C r/w clear all bits of lcd data. these bits affect segdio pins that are conigured as lcd drivers. this bi t does not auto clear. lcd_seg0[5:0] 2410[5:0] 0 C r/w seg data for seg0 lcd_seg1[5:0] 2411[5:0] 0 C r/w seg data for seg1 lcd_seg2[5:0] 2412[5:0] 0 C r/w seg data for seg2 lcd_seg3[5:0] 2413[5:0] 0 C r/w seg data for seg3 lcd_seg4[5:0] 2414[5:0] 0 C r/w seg data for seg4 lcd_seg5[5:0] 2415[5:0] 0 C r/w seg data for seg5 lcd_seg6[5:0] 2416[5:0] 0 C r/w seg data for seg6 lcd_seg7[5:0] 2417[5:0] 0 C r/w seg data for seg7 lcd_seg8[5:0] 2418[5:0] 0 C r/w seg data for seg8 downloaded from: http:///
maxim integrated 57 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description lcd_seg9[5:0] 2419[5:0] 0 C r/w seg data for seg9 lcd_seg10[5:0] 241a[5:0] 0 C r/w seg data for seg10 lcd_seg11[5:0] 241b[5:0] 0 C r/w seg data for seg11 lcd_seg12[5:0] 241c[5:0] 0 C r/w seg data for seg12 lcd_seg13[5:0] 241d[5:0] 0 C r/w seg data for seg13 lcd_seg14[5:0] 241e[5:0] 0 C r/w seg data for seg14 lcd_seg15[5:0] 241f[5:0] 0 C r/w seg data for seg15 lcd_seg16[5:0] 2420[5:0] 0 C r/w seg data for seg16 lcd_seg17[5:0] 2421[5:0] 0 C r/w seg data for seg17 lcd_seg18[5:0] 2422[5:0] 0 C r/w seg data for seg18 lcd_seg19[5:0] 2423[5:0] 0 C r/w seg data for seg19 lcd_seg20[5:0] 2424[5:0] 0 C r/w seg data for seg20 lcd_seg21[5:0] 2425[5:0] 0 C r/w seg data for seg21 lcd_seg22[5:0] 2426[5:0] 0 C r/w seg data for seg22 lcd_seg23[5:0] 2427[5:0] 0 C r/w seg data for seg23 lcd_seg24[5:0] 2428[5:0] 0 C r/w seg data for seg24 lcd_seg25[5:0] 2429[5:0] 0 C r/w seg data for seg25 lcd_seg26[5:0] 242a[5:0] 0 C r/w seg data for seg26 lcd_seg27[5:0] 242b[5:0] 0 C r/w seg data for seg27 lcd_seg28[5:0] 242c[5:0] 0 C r/w seg data for seg28 lcd_seg29[5:0] 242d[5:0] 0 C r/w seg data for seg29 lcd_seg30[5:0] 242e[5:0] 0 C r/w seg data for seg30 lcd_seg31[5:0] 242f[5:0] 0 C r/w seg data for seg31 lcd_seg32[5:0] 2430[5:0] 0 C r/w seg data for seg32 lcd_seg33[5:0] 2431[5:0] 0 C r/w seg data for seg33 lcd_seg34[5:0] 2432[5:0] 0 C r/w seg data for seg34 lcd_seg35[5:0] 2433[5:0] 0 C r/w seg data for seg35 lcd_seg36[5:0] 2434[5:0] 0 C r/w seg data for seg36 lcd_seg37[5:0] 2435[5:0] 0 C r/w seg data for seg37 lcd_seg38[5:0] 2436[5:0] 0 C r/w seg data for seg38 lcd_seg39[5:0] 2437[5:0] 0 C r/w seg data for seg39 lcd_seg40[5:0] 2438[5:0] 0 C r/w seg data for seg40 lcd_seg41[5:0] 2439[5:0] 0 C r/w seg data for seg41 lcd_seg42[5:0] 243a[5:0] 0 C r/w seg data for seg42 lcd_seg43[5:0] 243b[5:0] 0 C r/w seg data for seg43 lcd_seg44[5:0] 243c[5:0] 0 C r/w seg data for seg44 lcd_seg45[5:0] 243d[5:0] 0 C r/w seg data for seg45 lcd_seg46[5:0] 243e[5:0] 0 C r/w seg data for seg46 lcd_seg47[5:0] 243f[5:0] 0 C r/w seg data for seg47 lcd_seg48[5:0] 2440[5:0] 0 C r/w seg data for seg48 lcd_seg49[5:0] 2441[5:0] 0 C r/w seg data for seg49 lcd_seg50[5:0] 2442[5:0] 0 C r/w seg data for seg50 lcd_seg51[5:0] 2443[5:0] 0 C r/w seg data for seg51 lcd_seg52[5:0] 2444[5:0] 0 C r/w seg data for seg52 lcd_seg53[5:0] 2445[5:0] 0 C r/w seg data for seg53 lcd_seg54[5:0] 2446[5:0] 0 C r/w seg data for seg54 lcd_seg55[5:0] 2447[5:0] 0 C r/w seg data for seg55 downloaded from: http:///
maxim integrated 58 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description lcd_vmode[1:0] 2401[7:6] 00 00 r/w speciies how v lcd is generated. lcd_vmode description 11 external v lcd 10 lcd dac enabled 01 lcd dac enabled 00 no dac. v lcd = v3p3l. lcd_y 2400[2] 0 C r/w lcd blink frequency (ignored if blink is disabled).1 = 1 hz, 0 = 0.5 hz mpu_div[2:0] 2200[2:0] 0 0 r/w mpu clock rate is: mpu rate = mck rate x 2 -(2+mpu_div[2:0]) . the maximum value for mpu_div[2:0] is 4. based on the default values of the pll_fast bit and mpu_div[2:0], the power up mpu rate is 6.29mhz/4 = 1.5725mhz. the minimum mpu clock rate is 38.4khz when pll_fas t = 1. mux2_sel[3:0] 2104[3:0] 0 0 r/w selects which adc input is to be converted during time slot 2. mux3_sel[3:0] 2104[7:4] 0 0 r/w selects which adc input is to be converted during time slot 3. mux4_sel[3:0] 2103[3:0] 0 0 r/w selects which adc input is to be converted during time slot 4. mux5_sel[3:0] 2103[7:4] 0 0 r/w selects which adc input is to be converted during time slot 5. mux6_sel[3:0] 2102[3:0] 0 0 r/w selects which adc input is to be converted during time slot 6. mux7_sel[3:0] 2102[7:4] 0 0 r/w selects which adc input is to be converted during time slot 7. mux8_sel[3:0] 2101[3:0] 0 0 r/w selects which adc input is to be converted during time slot 8. mux9_sel[3:0] 2101[7:4] 0 0 r/w selects which adc input is to be converted during time slot 9. mux10_sel[3:0] 2100[3:0] 0 0 r/w selects which adc input is to be converted during time slot 10. mux_div[3:0] 2100[7:4] 0 0 r/w mux_div[3:0] is the number of adc time slots in each mux frame. the maximum number of time slots is 11. opt_bb 2457[0] 0 C r/w conigures the input of the optical port to be a dio pin to allow it to be bit-banged. in this case, dio5 becomes a third high speed uart. opt_fdc[1:0] 2457[5:4] 0 C r/w selects opt_tx modulation duty cycle. opt_fdc function 00 50% low 01 25% low 10 12.5% low 11 6.25% low opt_rxdis 2457[2] 0 C r/w opt_rx can be conigured as an input to the optical uart or as segdio55. opt_rxdis = 0 and lcd_map[55] = 0: opt_rx opt_rxdis = 1 and lcd_map[55] = 0: dio55 opt_rxdis = 0 and lcd_map[55] = 1: seg55 opt_rxdis = 1 and lcd_map[55] = 1: seg55 opt_rxinv 2457[1] 0 C r/w inverts result from opt_rx comparator when 1. affects only the uart input. has no effect when opt_rx is used as a dio input. opt_txe [1:0] 2456[3:2] 00 C r/w conigures the opt_tx output pin.if lcd_map[51] = 0: 00 = dio51, 01 = opt_tx, 10 = wpulse, 11 = varpulse if lcd_map[51] = 1: xx = seg51 opt_txinv 2456[0] 0 C r/w invert opt_tx when 1. this inversion occurs before modulation. opt_txmod 2456[1] 0 C r/w enables modulation of opt_tx. when opt_txmod is set, opt_tx is modulated when it would otherwise have been zero. the modulation is applied after any inversion caused by opt_txinv. osc_comp 28a0[5] 0 C r/w enables the automatic update of the pq rtc compensation value every time the temperature is measured. out_sq[1:0] 2200[7:6] 0 0 r/w deines the square wave output on segdio15 (if out_sqe=1) 00 C off 01 C 3.2768mhz 10 C 4.9152mhz 11 C 9.83mhz out_sqe 2458[4] 0 0 r/w enables the square wave output on segdio15. pb_state sfr f8[0] 0 0 r the de-bounced state of the pb pin. downloaded from: http:///
maxim integrated 59 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description perr_rdperr_wr sfr fc[6]sfr fc[5] 0 0 r/w the ic sets these bits to indicate that a parity error on the remote sensor has been detected. once set, the bits are remembered until they are cleared by the mpu. pll_ok sfr f9[4] 0 0 r indicates that the clock generation pll is settled. pll_fast 2200[4] 0 0 r/w controls the speed of the pll and mck. 1 = 19.66 mhz (xtal x 600) 0 = 6.29mhz (xtal x 192) pls_maxwidth[7:0] 210a[7:0] ff ff r/w pls_maxwidth[7:0] determines the maximum width of the pulse (low-going pulse if pls_inv = 0 or high-going pulse if pls_inv = 1). the maximum pulse width is (2 x pls_maxwidth[7:0] + 1) x ti. where ti is pls_ interval[7:0] in units of ck_fir clock cycles. if pls_interval[7:0] = 0 or pls_maxwidth[7:0] = 255, no pulse width checking is performed and the output pulses have 50% duty cycle. pls_ interval[7:0] 210b[7:0] 0 0 r/w pls_interval[7:0] determines the interval time between pulses. the time between output pulses is pls_ interval[7:0] x 4 in units of ck_fir clock cycles. if pls_interval[7:0] = 0, the fifo is not used and pulses are output as soon as the ce issues them. pls_interval[7:0] is calculated as follows: pls_interval[7:0] = floor ( mux frame duration in ck_fir cycles/ ce pulse updates per mux frame/4 ) for example, since the 71m654xt ce code is written to generate 6 pulses in one integration interval, when the fifo is enabled (i.e., pls_interval[7:0] 0) and that the frame duration is 1950 ck_fir clock cycles, pls_i nterval[7:0] should be written with floor(1950/6/4) = 81 so that the ive pulses are evenly spaced in time over th e integration interval and the last pulse is issued just prior to the end of the interval. pls_inv 210c[0] 0 0 r/w inverts the polarity of wpulse, varpulse, xpulse and ypulse. normally, these pulses are active low. when inverted, they become active high. port_e 270c[5] 0 0 r/w enables outputs from the pins segdio0-segdio15. port_e = 0 after reset and power-up blocks the momentary output pulse that would occur on segdio0 to segdio15. pq[20:0] 2886[4:0]2887[7:0] 2888[7:0] 0 0 r temperature compensation value computed by the quadratic compensation formula. pqmask 2511[2:0] 0 0 r/w sets the length of the pq mask. the mask is anded with the last four bits of pq according to the table below. pqmask also determines the length of pulse_auto in tmux. pqmask mask pulse_auto width 000 0000 1s 001 1000 2s 010 1100 4s 011 1110 8s 100 1111 16s pre_e 2704[5] 0 0 r/w enables the 8x preampliier. preboot sfrb2[7] C C r indicates that preboot sequence is active. rcmd[4:0] sfr fc[4:0] 0 0 r/w when the mpu writes a non-zero value to rcmd[4:0], the ic issues a command to the appropriate remote sensor. when the command is complete, the ic clears rcmd[4:0]. reset 2200[3] 0 0 w when set, writes a one to wf_rstbit and then causes a reset. rfly_dis 210c[3] 0 0 r/w controls how the ic drives the power pulse for the 71m6x03. when set, the power pulse is driven high and low. when cleared, it is driven high followed by an open circuit ly-back interval. rmt2_e 2709[3] 0 0 r/w enables the remote interface. rmt4_e 2709[4] 0 0 r/w enables the remote interface. rmt6_e 2709[5] 0 0 r/w enables the remote interface. rmt_rd[15:8] rmt_rd[7:0] 2602[7:0]2603[7:0] 0 0 r response from remote read request. rtc_fail 2890[4] 0 0 r/w indicates that a count error has occurred in the rtc and that the time is not trustworthy. this bit can be cleared by writing a 0. rtc_rd 2890[6] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu reads. when rtc_rd is read, it returns the status of the shadow register: 0 = up to date, 1 = frozen. rtc_sbsc[7:0] 2892[7:0] C C r time remaining until the next 1 second boundary. lsb = 1/256 second. rtc_tmin[5:0] 289e[5:0] 0 C r/w the target minutes register. see rtc_thr below. downloaded from: http:///
maxim integrated 60 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description rtc_thr[4:0] 289f[4:0] 0 C r/w the target hours register. the rtc_t interrupt occurs when rtc_min becomes equal to rtc_tmin and rtc _hr becomes equal to rtc_thr. rtc_wr 2890[7] 0 0 r/w freezes the rtc shadow register so it is suitable for mpu writes. when rtc_wr is cleared, the contents of the shadow register are written to the rtc counter on the next rtc clock (~500 hz). when rtc_wr is read, it returns 1 as long as rtc_wr is set. it continues to return one until the rtc counter actually updates. rtc_sec[5:0] rtc_min[5:0] rtc_hr[4:0] rtc_day[2:0] rtc_date[4:0] rtc_mo[3:0] rtc_yr[7:0] 2893[5:0]2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] CC C C C C C CC C C C C C r/w the rtc interface registers. these are the year, month, day, hour, minute and second parameters for the rtc. the rtc is set by writing to these registers. year 00 and all others divisible by 4 are deined as a leap year. sec 00 to 59 min 00 to 59 hr 00 to 23 (00 = midnight) day 01 to 07 (01 = sunday) date 01 to 31 mo 01 to 12 yr 00 to 99 each write operation to one of these registers must be preceded by a write to 0x20a0. rtm_e 2106[1] 0 0 r/w real time monitor enable. when 0, the rtm output is low. rtm0[9:8] rtm0[7:0] rtm1[7:0] rtm2[7:0] rtm3[7:0] 210d[1:0] 210e[7:0] 210f[7:0] 2110[7:0] 2111[7:0] 00 0 0 0 00 0 0 0 r/w four rtm probes. before each ce code pass, the values of these registers are serially output on the rtm pin. the rtm registers are ignored when rtm_e = 0. note that rtm0 is 10 bits wide. the others assume the upper two bits are 00. sbase:[10:0] 2519[2:0] 251a[7:0] 0 0 r/w base temperature for limit checking secure sfr b2[6] 0 0 r/w inhibits erasure of page 0 and lash addresses above the beginning of ce code as deined by ce_lctn[6: 0] for 71m6543gt/ght and ce_lctn[5:0] for 71m6543ft/ht. also inhibits the read of lash via the spi and ice port. sfilt 251d[3:0] 0 0 r/w filter variable for wake on temperature extremes. sleep 28b2[7] 0 0 w puts the part to slp mode. ignored if system power is present. the part wakes when the wake timer expires, when push button is pushed, or when system power returns. slot_ext[3:0] 2112[3:0] 0 0 r/s if non-zero, will extend the duration of time slot zero by up to 15 extra crystal cycles. the adc result for time slot zero will be left-shifted nine bits if slot_ext=0 and four bits if slot_ext0. smax[6:0] 251b[6:0] 0 0 r/w maximum temperature for limit checking smin[6:0] 251c[6:0] 0 0 r/w minimum temperature for limit checking spi_cmd[7:0] sfr fd[7:0] C C r spi command register for the 8-bit command from the bus master. spi_e 270c[4] 1 1 r/w spi port enable. enables spi interface on pins segdio36 C segdio39. requires that lcd_map[36-39] = 0. spi_safe 270c[3] 0 0 r/w limits spi writes to spi_cmd and a 16-byte region in dram. no other writes are permitted. spi_stat[7:0] 2708[7:0] 0 0 r spi_stat contains the status results from the previous spi transaction. bit 7: ready error: the 71m654xt was not ready to read or write as directed by the previous command. bit 6: read data parity: this bit is the parity of all bytes read from the 71m654xt in the previous command. does not include the spi_stat byte. bit 5: write data parity: this bit is the overall parity of the bytes written to the 71m654xt in the previous command. it includes cmd and addr bytes. bit 4-2: bottom 3 bits of the byte count. does not include addr and cmd bytes. one, two, and three byte instructions return 111. bit 1: spi flash mode: this bit is zero when the test pin is zero. bit 0: spi flash mode ready: used in spi flash mode. indicates that the lash is ready to receive ano ther write instruction. stemp[15:0] 2881[7:0]2882[7:0] C C r the result of the temperature measurement. sum_samps[12:8]sum_samps[7:0] 2107[4:0]2108[7:0] 0 0 r/w the number of multiplexer cycles per xfer_busy interrupt. maximum value is 8191 cycles. tc_a[9:0] 2508[1:0]2509[7:0] 0 0 r/w temperature compensation factor for quadratic compensation. tc_b[11:0] 250a[3:0]205b[7:0] 0 0 r/w temperature compensation factor for quadratic compensation. tc_c[11:0] 289c[3:0]289d[7:0] 0 0 r/w temperature compensation factor for quadratic compensation. temp_22[12:8]temp_22[7:0] 230a[4:0]230b[7:0] 0 C r storage location for stemp at 22nc. stemp is an 11-bit word. downloaded from: http:///
maxim integrated 61 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) name location rstwk dir description temp_bat 28a0[4] 0 C r/w causes v bat to be measured whenever a temperature measurement is performed. temp_bsel 28a0[7] 0 C r/w selects which battery is monitored by the temperature sensor: 1 = v bat , 0 = v bat_rtc tbyte_busy 28a0[3] 0 0 r indicates that hardware is still writing the 0x28a0 byte. additional writes to this byte will be locked out while it is one. write duration could be as long as 6ms. temp_per[2:0] 28a0[2:0] 0 C r/w sets the period between temperature measurements. automatic measurements can be enabled in any mode (msn, brn, lcd, or slp). temp_per = 0 disables automatic temperature updates, in which case temp_start may be used by the mpu to initiate a one-shot temperature measurement. temp_per time (s) 0 no temperature updates 1-6 2 (3+temp_per) 7 continuous updates in automatic mode, temp_start is the indicator for the temperature sensor status: temp_start = 1 (temperature sensor is busy, cannot measure temperature) temp_start = 0 (temperature sensor is idle, can measure temperature) temp_pwr 28a0[6] 0 C r/w selects the power source for the temp sensor:1 = v v3p3d , 0 = v bat_rtc . this bit is ignored in slp and lcd modes, where the temp sensor is always powered by v bat_rtc . temp_start 28b4[6] 0 0 r/w when temp_per = 0 automatic temperature measurements are disabled, and temp_start may be set by the mpu to initiate a one-shot temperature measurement. in automatic mode, temp_start is the indicator for the temperature sensor status: temp_start = 1 (temperature sensor is busy, cannot measure temperature) temp_start = 0 (temperature sensor is idle, can measure temperature) temp_start is ignored in slp and lcd modes. hardware clears temp_start when the temperature measurement is complete. tmux[5:0] 2502[5:0] C C r/w selects one of 32 signals for tmuxout. tmux2[4:0] 2503[4:0] C C r/w selects one of 32 signals for tmux2out. tmuxra[2:0] 270a[2:0] 000 000r/w the tmux setting for the remote isolated sensor (71m6x03). umux_sel 2456[4] 0 0 r/w selects uart1 io pins. selects opt_tx and opt_rx when 0. selects segdio17 and segdio16 when 1. if umux_sel = 0, segdio17, and segdio16 are standard dio pins, relecting the value of lcd_segdio16[5 :0] and lcd_segdio17[5:0]. vref_cal 2704[7] 0 0 r/w brings the adc reference voltage out to the v ref pin. this feature is disabled when vref_dis=1. vref_dis 2704[6] 0 1 r/w disables the internal adc voltage reference. vstat[2:0] sfr f9[2:0] C C r this word describes the source of power and the status of v dd . 000 system power ok. v v3p3a >3.0v. analog modules are functional and accurate. [v3aok,v3ok] = 11 001 system power low. 2.8v2.25v. full digital functionality. [v3aok,v3ok] = 00, [vddok,vddgt2] = 11 011 battery power and v dd >2.0. flash writes are inhibited. if the trimvdd[5] fuse is blown, pll_fast (i/o ram 0x2200[4]) is cleared. [v3aok,v3ok] = 00, [vddok,vddgt2] = 01 101 battery power and v dd <2.0. when vstat=101, processor is nearly out of voltage. processor failure is imminent.[v3aok,v3ok] = 00, [vddok,vddgt2] = 00 wake_arm 28b2[5] 0 C r/w arms the wake timer and loads it with wake_tmr[7:0]. when sleep or lcd_only is asserted by the mpu, the wake timer becomes active. wake_tmr[7:0] 2880[7:0] 0 C r/w timer duration is wake_tmr+1 seconds. wd_rst 28b4[7] 0 0 w reset the wd timer. the wd is reset when a 1 is written to this bit. writing a one clears and restarts the watch dog timer. wf_dio4 28b1[2] 0 C r dio4 wake lag bit. if dio4 is conigured to wake the part, this bit is set whenever the de-bounced version of dio4 rises. it is held in reset if di04 is not conigured for wakeup. wf_dio52 28b1[1] 0 C r dio52 wake lag bit. if dio52 is conigured to wake the part, this bit is set whenever the de-bounced version of dio52 rises. it is held in reset if di052 is not conigured for wakeup. downloaded from: http:///
maxim integrated 62 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 13. i/o ram locations in alphabetical order (continued) meter calibration once the 71m654xt energy meter device has been installed in a meter system, it must be calibrated. a com - plete calibration includes: ? establishment of the reference temperature (typically 22c). ? calibration of the metrology section: calibration for toler - ances of the current sensors, voltage dividers and sig - nal conditioning components as well as of the internal reference voltage (v ref ) at the reference temperature. the metrology section can be calibrated using the gain and phase adjustment factors accessible to the ce. the gain adjust ment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies. due to the flexibility of the mpu firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented. it is also possible to implement segment-wise calibration (depending on cur - rent range). the 71m6543ft/ht/gt/ght support common industry standard calibration techniques, such as single-point (energy-only), multipoint (energy, v rms , i rms ), and auto- calibration.contact maxim integrated to obtain a copy of the latest calibration spreadsheet file for the 71m654xt. firmware interface overview: functional order the i/o ram locations at addresses 0x2000 to 0x20ff have sequential addresses to facilitate reading by the mpu. these i/o ram locations are usually modified only at power-up. these addresses are an alternative sequen - tial address to subsequent addresses (above 0x2100). for instance, equ[2:0] can be accessed at i/o ram 0x2000[7:5] or at i/o ram 0x2106[7:5]. unimplemented (u) and reserved (r) bits are shaded in light gray. unimplemented bits are identified with a u. unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. reserved bits are identified with an r, and must always be written with a zero. writing values other than zero to reserved bits may have undesirable side effects and must be avoided. nonvolatile bits are shaded in dark gray. nonvolatile bits are backed up during power failures if the system includes a battery connected to the v bat pin. i/o ram map: details writable bits are written by the mpu into configuration ram. typically, they are initially stored in flash memory and copied to the configuration ram by the mpu. some of the more frequently programmed bits are mapped to the mpu sfr memory space. the remaining bits are mapped to the address space 0x2xxx. the rst and wk columns describe the bit values upon reset and wake, respectively. no entry in one of these columns means the bit is either read-only or is powered by the nv supply and is not initial - ized. write-only bits return zero when they are read. locations that are shaded in grey are nonvolatile (i.e., battery-backed). name location rstwk dir description wf_dio55 28b1[0] 0 C r dio55 wake lag bit. if dio55 is conigured to wake the part, this bit is set whenever the de-bounced version of dio55 rises. it is held in reset if di055 is not conigured for wakeup. wf_temp 28b1[6] 0 C r indicates that the temperature range check hardware caused the part to wake up. wake_arm 28b2[5] 0 C r/w arms the wake timer and loads it with wake_tmr[7:0]. when sleep or lcd_only is asserted by the mpu, the wake timer becomes active. wf_pb 28b1[3] C C r indicates that the pb caused the part to wake. wf_rx 28b1[4] 0 C r indicates that rx caused the part to wake. wf_cstart wf_rst wf_rstbit wf_ovf wf_erst wf_badvdd 28b0[7]28b0[6] 28b0[5] 28b0[4] 28b0[3] 28b0[2] 01 0 0 0 0 C r indicates that the reset pin, reset bit, erst pin, watchdog timer, the cold start detector, or bad v bat caused the part to reset. downloaded from: http:///
maxim integrated 63 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com reading the info page information useful for calibrating the temperature sensor and other functions is available in trim fuses. the trim fuse values provided in the 71m6543t and 71m6543gt devices cannot be directly accessed through the i/o ram space. they reside in a special area termed the info page. the mpu gains access to the info page by setting the info_pg (i/o ram 0x270b[0]) control bit. once this bit is set, info page contents are accessible in program memory space starting at the address speci - fied by the contents of ce_lctn[6:0] (71m6543gt) or ce_lctn[5:0] (71m6543t) (i/o ram 0x2109[6:0] for 71m6543ght or 0x2109[5:0] for 71m6543ht). these pointers specify a base address at a 1kb address bound - ary, which is at 1024 x ce_lctn[6:0] (71m6543gt) or ce_lctn[5:0] (71m6543t). table 14 l ists of the avail - able trim fuses and their corresponding offsets relative to the info page base address. after reading the desired info page information, the mpu must reset the info_ pg bit. the code below provides an example for reading info page fuse trims. in this code example, the address, px is a pointer to the mpus code space. in assembly lan - guage, the info page data objects, which are read-only, must be accessed with the movc 8051 instruction. in c, info page trim fuses must be fetched with a pointer of the correct width, depending whether an 8-bit or a 16-bit data object is to be fetched. the case statements in the code example below perform casts to obtain a pointer of the correct size for each object, as needed. in assembly language, the mpu has to form 11-bit or 16-bit values from two separate 8-bit fetches, depending on the object being fetched. the byte values containing less than 8 valid bits are lsb justified. for example info page offset 0x90 is an 8-bit object, whose three lsbs are bits [10:8] of the complete temp_85[10:0] 11-bit object. the info page data objects are 2s complement format and should be sign extended when read into a 16-bit data type (see case _temp85 in the code example). #if high_precision_meter int16_t read_trim (enum etrimsel select) { uint8r_t *px; int16_t x; px = ((uint16_t)select) + ((uint8r_t *)(ce3 << 10)); switch (select) { default: case _trimbgd: info_pg = 1; x = *px; info_pg = 0; break; case _trimbgb: info_pg = 1; x = *(uint16r_t*)px; info_pg = 0; break; case _temp85: info_pg = 1; x = *(uint16r_t*)px; info_pg = 0; if (x & 0x800) x |= 0xf800; break; } return (x); } #endif //#if high_precision_meter table 14. register and fuses for temperature sensing register name definition location address format typical value stemp_t85_p stemp at +85c info block 0xaa, 0xab 16 bits, signed 4400 stemp_t22_p stemp at +22c info block 0x8a, 0x8b 13 bits, unsigned 3600 t85_p probe temperature at +85c info block 0xa6, 0xa7 16 bits signed 605 t22_p probe temperature at +22c info block 0x9a 8 bits signed 35 temp_85 ? stemp trim for high accuracy (h) parts info block 0x90, 0x91 11 bits, sign extended stemp temperature sensor i/o ram 0x2882, 0x2882 11 bits, sign extended ? not used for temperature sensing. used for vref compensation in high accuracy parts. downloaded from: http:///
maxim integrated 64 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com ce interface descriptionce program the ce performs the precision computations necessary to accurately measure energy. these computa tions include offset cancellation, phase compensation, product smooth - ing, product summation, frequency detection, var calcula - tion, sag detection and voltage phase measurement. the ce program is supplied by maxim integrated as a data image that can be merged with the mpu operational code for meter applications. typically, the ce program provided with the demonstration code covers most appli - cations and does not need to be modified. other varia - tions of ce code are available. contact your local maxim integrated representative to obtain the appropriate ce code required for a specific application. ce data format all ce words are 4 bytes. unless specified otherwise, they are in 32-bit twos complement format (-1 = 0xffffffff). calibration para meters are defined in flash memory (or external eeprom) and must be copied to ce data memory by the mpu before enabling the ce. internal variables are used in internal ce calculations. input variables allow the mpu to control the behavior of the ce code. output variables are outputs of the ce cal - culations. the corresponding mpu address for the most signi ficant byte is given by 0x0000 + 4 x ce_address and by 0x0003 + 4 x ce_address for the least significant byte. constants ? sampling frequency: 2520.62hz. ? f 0 : frequency of the mains phases (typically 50hz or 60hz). ? imax: rms current corresponding to 250mv peak (176.8 mvrms) at the inputs ia and ib. imax needs to be adjusted if the preamplifier is activated for the iap-ian inputs. for a 250? shunt resistor, imax becomes 707a (176.8 mvrms/250fi = 707.2arms). ? vmax: rms voltage corresponding to 250mv peak at the va and vb inputs. ? n acc : accumulation count for energy measurements is sum_samps[12:0]. the duration of the accumu - lation interval for energy measurements is sum_ samps[12:0]/f s . ? x: gain constant of the pulse generators. its value is determined by pulse_fast and pulse_slow. ? voltage lsb (for sag threshold) = vmax x 7.8798 x10 -9 v. the system constants imax and vmax are used by the mpu to convert internal digital quantities (as used by the ce) to external, i.e., metering quantities. their values are determined by the scaling of the voltage and current sen - sors used in an actual meter. environment before starting the ce using the ce_e bit (i/o ram 0x2106[0]), the mpu has to establish the proper environ - ment for the ce by implementing the following steps: ? locate the ce code in flash memory using ce_lctn[6:0] (71m6543gt/ght or ce_lctn[5:0] (71m6543ft/ht). ? load the ce data into ram. ? establish the equation to be applied in equ[2:0]. ? establish the number of samples per accumulation period in sum_samps[12:0]. ? establish the number of cycles per adc multiplexer frame (mux_div[3:0]). ? apply proper values to muxn_sel, as well as proper selections for diffn_e and rmt_e in order to config - ure the analog inputs. ? initialize any mpu interrupts, such as ce_busy, xfer_busy, or the power failure detection interrupt. ? vmax = 600v, imax = 707a, and kh = 1wh/pulse are assumed as default settings when different ce codes are used, a different set of envi - ronment parameters need to be established. the exact values for these parameters are listed in the application notes and other documentation which accompanies the ce code. the ce details described in this data sheet should be considered typical and may not, in aggregate, be indicative of any particular ce code. contact your maxim integrated representative for details about available stan - dard ce codes.ce calculations the mpu selects the basic configuration for the ce by setting the equ variable. ce input data data from the afe is placed into ce memory by hardware at adc0-adc10. table 16 describes the process. downloaded from: http:///
maxim integrated 65 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 15. power equations table 16. ce raw data access locations * remote interface data. ce status and control the cestatus register (0x80) contains bits that reflect the status of the signals that are applied to the ce. ceconfig (0x20) contains bits that control basic opera - tion of the compute engine. the ce code supports registers to establish the sag threshold and gain for each of the input channels. when the input rms voltage level falls below an established level, a warning is posted to the mpu. this level is called the sag threshold, and it is set in the sag_thr register. gain for each channel is adjusted in the gain_adj0 (voltage), gain_adj1 (current channel a) and gain_ adj2 (current channel b). transfer variables after each pass through ce program code, the ce asserts a xfer_busy interrupt. this informs the mpu that new data is available. it is the responsibility of mpu code to retrieve the data from the ce in a timely manner. equ[2:0] watt and var formula ( wsum/varsum ) w0sum/ var0sum w1sum/ var1sum w2sum/ var2sum i0sq sum i1sq sum i2sq sum 3 va x (ia-ib/2) + vc x ic (2 element 4w 3 f delta) va x (ia-ib)/2 vc x ic ia-ib ib ic 4 va x (ia-ib)/2 + vb(ic-ib)/2 (2 element 4w 3 f wye) va x (ia-ib)/2 vb x (ic-ib) ia-ib ic-ib ic 5 va x ia+vb x ib + vc x ic (3 element 4w 3 f wye) va x ia vb x ib vc x ic ia ib ic pin muxn_sel handle ce ram location diff0_e diff0_e 0 1 0 1 iadc0 0 0 0 0 iadc1 1 1 rmt2_e, diff2_e rmt2_e, diff2_e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc2 2 2 - - 2 2 2* 2* iadc3 3 3 rmt4_e, diff4_e rmt4_e, diff4_e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc4 4 4 - - 4 4 4* 4* iadc5 5 5 rmt6_e, diff6_e rmt6_e, diff6_e 0,0 0,1 1,0 1,1 0,0 0,1 1,0 1,1 iadc6 6 6 - - 6 6 6* 6* iadc7 7 7 there are no coniguration bits for vadc8, 9, 10 vadc8 (va) 8 8 vadc9 (vb) 9 9 vadc10 (vc) 10 10 ce flow diagrams downloaded from: http:///
maxim integrated 66 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 18. ce configuration register table 17. ce status register ceconfig bit name default description 22 ext_temp 0 when 1, the mpu controls temperature compensation via the gain_adjn registers (ce ram 0x40-0x42), when 0, the ce is in control. 21 edge_int 1 when 1, xpulse produces a pulse for each zero-crossing of the mains phase selected by freqsel[1:0] , which can be used to interrupt the mpu. 20 sag_int 1 when 1, activates ypulse output when a sag condition is detected. 19:8 sag_cnt 252(0xfc) the number of consecutive voltage samples below sag_thr (ce ram 0x24) before a sag alarm is declared. the default value is equivalent to 100 ms. 7:6 freqsel[1:0] 0 freqsel[1:0] selects the phase to be used for the frequency monitor, sag detection, and for the zero crossing counter (mainedge_x). freq sel[1:0] phase selected 0 0 a 0 1 b* 1 x not allowed 5 ext_pulse 1 when zero, causes the pulse generators to respond to internal data (wpulse = wsum_x, vpulse = varsum_x). otherwise, the generators respond to values the mpu places in apulsew and apulser. 4:2 reserved 0 reserved. 1 pulse_fast 0 when pulse_fast = 1, the pulse generator input is increased 16x. when pulse_slow = 1, the pulse generator input is reduced by a factor of 64. these two parameters control the pulse gain factor x (see table below). allowed values are either 1 or 0. default is 0 for both (x = 6). 0 pulse_slow 0 pulse_fast pulse_slow x 0 0 1.5 x 2 2 = 6 1 0 1.5 x 2 6 = 96 0 1 1.5 x 2 -4 = 0.09375 1 1 do not use cestatus bit name description 31:4 not used these unused bits are always zero. 3 f0 f0 is a square wave at the exact fundamental input frequency. 2 sag_c normally zero. becomes one when vb remains below sag_thr for sag_cnt samples. does not return to zero until vb rises above sag_thr. 1 sag_b normally zero. becomes one when vb remains below sag_thr for sag_cnt samples. does not return to zero until vb rises above sag_thr. 0 sag_a normally zero. becomes one when va remains below sag_thr for sag_cnt samples. does not return to zero until va rises above sag_thr. downloaded from: http:///
maxim integrated 67 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 19. sag threshold and gain adjustment registers table 20. ce transfer registers ce address name default description 0x24 sag_thr 2.39 x 10 7 the voltage threshold for sag warnings. the default value is equivalent to 113v peak or 80 vrms if vmax = 600vrms. rms 9 v2 sag_thr vmax 7.8798 10 ? ? = ?? 0x40 gain_adj0 16384 this register scales the voltage measurement channels vadc8 (va), vadc9 (vb) and vadc10 (vc). the default value of 16384 is equivalent to unity gain (1.000). 0x41 gain_adj1 16384 this register scales the iadc0-iadc1 current channel for neutral current. the default value of 16384 is equivalent to unity gain (1.000). 0x42 gain_adj2 16384 this register scales the ia current channel for phase a. the default value of 16384 is equivalent to unity gain (1.000). 0x43 gain_adj3 16384 this register scales the ib current channel for phase b. the default value of 16384 is equivalent to unity gain (1.000). 0x44 gain_adj4 16384 this register scales the ic current channel for phase c. the default value of 16384 is equivalent to unity gain (1.000). ce address name description 0x84? wsum_x the signed sum: w0sum_x+w1sum_x. not used for equ[2:0] = 0 and equ[2:0] = 1. 0x85 w0sum_x the sum of wh samples from each wattmeter element.lsb = 9.4045 x 10 -13 x vmax x imax wh (local) lsb = 1.55124 x 10 -12 x vmax x imax wh (remote) 0x86 w1sum_x 0x87 w2sum_x 0x88? varsum_x the signed sum: var0sum_x+var1sum_x. not used for equ[2:0] = 0 and equ[2:0] = 1. 0x89 var0sum_x the sum of varh samples from each wattmeter element. lsb = 9.4045 x 10 -13 x vmax x imax varh (local) lsb = 1.55124 x 10 -12 x vmax x imax varh (remote) 0x8a var1sum_x 0x8b var2sum_x 0x8c i0sqsum_x the sum of squared current samples from each element.lsb = 9.4045 x 10 -13 imax2 a 2 h (local) lsb = 2.55872 x 10 -12 x imax2 a 2 h (remote) 0x8d i1sqsum_x 0x8e i2sqsum_x 0x8f i3sqsum_x 0x90 v0sqsum_x the sum of squared voltage samples from each element.lsb= 9.4045 x 10 -13 vmax2 v 2 h (local) lsb= 9.40448 x 10 -13 x vmax2 v 2 h (remote) 0x91 v1sqsum_x 0x92 v2sqsum_x 0x82 freq_x fundamental frequency: 6 32 6 32 2520.6hz lsb 0.509 10 hz (for local) 2 2520.6hz lsb 0.587 10 hz (for remote) 2 ?? ? ? 0x83 mainedge_x the number of edge crossings of the selected voltage in the previous ac cumulation interval. edge crossings are either direction and are debounced. downloaded from: http:///
maxim integrated 68 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 21. ce pulse generation parameters ce address name default description 0x21 wrate 547 acc vmax imax k kh wh / pulse wrate n x ?? = ? ?? where:k = 66.1782 (local sensors) k = 109.1587 (remote sensor) n acc = sum_samps[12:0] ( ce ram 0x23 ) x is a factor determined by pulse_fast and pulse_slow. see ceconfig deinition for more information the default value yields 1.0 wh/pulse for vmax = 600 v and imax = 208 a. the maximum value for wrate is 32,768 (2 15 ). 0x22 kvar 6444 scale factor for var measurement. 0x23 sum_samps 2520 sum_samps (n acc ). 0x45 apulsew 0 wh pulse (wpulse) generator input to be updated by the mpu when using external pulse generation. the output pulse rate is: apulsew * f s * 2 -32 * wrate * x * 2 -14 . this input is buffered and can be updated by the mpu during a conversion interval. the change takes effect at the beginning of the next interval. 0x46 wpulse_ctr 0 wpulse counter. 0x47 wpulse_frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always counts up towards the next pulse. 0x48 wsum_accum 0 roll-over accumulator for wpulse. 0x49 apulser 0 varh (vpulse) pulse generator input. 0x4a vpulse_ctr 0 vpulse counter. 0x4b vpulse_frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always counts up towards the next pulse. 0x4c vsum_accum 0 roll-over accumulator for vpulse. downloaded from: http:///
maxim integrated 69 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 22. other ce parameters ce address name default description 0x25 quant_va 0 compensation factors for truncation and noise in voltage, current, real energy and reactive energy for phase a. 0x26 quant_ia 0 0x27 quant_a 0 0x28 quant_vara 0 0x29 ? quant_vb 0 compensation factors for truncation and noise in voltage, current, real energy and reactive energy for phase b. 0x2a quant_ib 0 0x2b quant_b 0 0x2c quant_varb 0 0x2d quant_vc 0 compensation factors for truncation and noise in voltage, current, real energy and reactive energy for phase c. 0x2e quant_ic 0 0x2f quant_c 0 0x30 quant_varc 0 0x38 0x43453431 ce ile name identiier in ascii format (ce41a01f). these values are overwritten as soon as the ce starts 0x39 0x6130316b 0x3a 0x00000000 lsb weights for use with local sensors: quant_ix_lsb = 5.08656 10 -13 imax 2 (amps 2 ) quant_wx_lsb = 1.04173 10 -9 vmax imax (watts) quant_varx_lsb = 1.04173 10 -9 vmax imax (vars) lsb weights for use with the 71m6x03 isolated sensors: quant_ix_lsb = 1.38392 10 -12 imax 2 (amps 2 ) quant_wx_lsb = 1.71829 10 -9 vmax imax (watts) quant_varx_lsb = 1.71829 10 -9 vmax imax (vars) downloaded from: http:///
maxim integrated 70 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com table 23. ce calibration parameters ce address name default description 0x10 cal_ia 16384 these constants control the gain of their respective channels. the nominal value for each parameter is 2 14 = 16384. the gain of each channel is directly proportional to its cal parameter. thus, if the gain of a channel is 1% slow, cal should be increased by 1%. refer to the 71m6x03 demo board users manual for the equations to calculate these calibration parameters. 0x11 cal_va 16384 0x13 cal_ib 16384 0x14 cal_vb 16384 0x12 phadj_a 0 these constants control the ct phase compensation. com pensation does not occur when phadj_x = 0. as phadj_x is increased, more compensation (lag) is introduced. the range is p 215C1. if it is desired to delay the current by the angle f , the equations are: at 60hzat 50hz 0x15 phadj_b 0 0x18 phadj_c 0 0x12 l_comp2_a 16384 the shunt delay compensation is obtained using the equation provided below:where: f s = sampling frequency f = main frequency 0x15 l_comp2_b 16384 0x18 l_comp2_c 16384 downloaded from: http:///
maxim integrated 71 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com pulse generation wrate (ce ram 0x21) along with the pulse_slow and pulse_fast bits control the number of pulses that are generated per measured wh and varh quantities. the pulse rate is proportional to the wrate value for a given energy. the meter constant kh is derived from wrate as the amount of energy measured for each pulse. that is, if kh = 1wh/pulse, a power applied to the meter of 120 v and 30 a results in one pulse per second; if the load is 240 v at 150 a, ten pulses per second are generated. normally, the ce takes the values from w0sum_x and var0sum_x and moves them to apulsew and apulser, respectively. then, pulse generation logic in the ce creates the actual pulses. however, the mpu can take direct control of the pulse generation process by setting ext_pulse = 1. in this case, the mpu sets the pulse rate by directly loading apulsew and apulser. note that since creep management is an mpu function, when the ce manages pulse output (ext_pulse = 0) creep management is disabled. the maximum pulse rate is 3 x f s = 7.56khz. the maximum time jitter is 1/6 of the multiplexer cycle period (nominally 67s) and is independent of the num - ber of pulses measured. thus, if the pulse generator is monitored for one second, the peak jitter is 67ppm. after 10 seconds, the peak jitter is 6.7ppm. the average jit - ter is always zero. if it is attempted to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without exhibiting any rollover char - acteristics. the actual pulse rate, using wsum as an example, is: s 46 wrate wsum f x rate hz 2 ? ?? = where f s = sampling frequency (2520.6 hz), x = pulse speed factor derived from the ce variables pulse_ slow and pulse_fast. ce flow diagrams figure 20 , figure 21 , and figure 22 show the data flow through the ce in simplified form. functions not shown include delay compensation, sag detection, scaling, and the processing of meter equations. figure 20. ce data flow ? multiplexer and adc decima to r demultiplexer ? mod vref f s = 2184h zf s = 2184hz ib mu lt iplexer vb ic vc id ia va ib_r aw vb_raw ic_r aw vc_raw id_r aw ia_r aw va _r aw downloaded from: http:///
maxim integrated 72 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com figure 21. ce data flow ? offset, gain, and phase compensation figure 22. ce data flow ? squaring and summation offset null cal_ia phase comp lpf w0 lpf va r0 90 i0 phadj_0 f0 ia_raw offset null cal_va v0 gain_adj f0 va _r aw f0 f0 genera to r ...other phases wa wasum_x wb wbsum_x wc wcsum_x va ra va rasum_x va rb va rbsum_x va rc va rcsum_x sum iasqsum_x iasq i 2 v 2 ia ibsqsum_x ibsq ib icsqsum_x icsq ic vasqsum_x vasq va vbsqsum_x vbsq vb vcsqsum_x vcsq vc idsqsum_x idsq id f0 f0 square mpu sum_sams = 2184 downloaded from: http:///
maxim integrated 73 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com ordering information f = lead(pb)-free/rohs-compliant package. r = tape and reel. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range accuracy (typ, %) flash (kb) pin-package 71m6543ft -igt/f -40 c to +85 c 0.1 64 100 lqfp 71m6543ft-igtr/f -40 c to +85 c 0.1 64 100 lqfp 71m6543ht -igt/f -40 c to +85 c 0.1 64 100 lqfp 71m6543ht-igtr/f -40 c to +85 c 0.1 64 100 lqfp 71m6543gt -igt/f -40 c to +85 c 0.1 128 100 lqfp 71m6543gt-igtr/f -40 c to +85 c 0.1 128 100 lqfp 71m6543ght -igt/f -40 c to +85 c 0.1 128 100 lqfp 71m6543ght-igtr/f -40 c to +85 c 0.1 128 100 lqfp package type package code outline no. land pattern no. 100 lqfp c100l+8 21-0684 90-0416 downloaded from: http:///
maxim integrated 74 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics www.maximintegrated.com typical operating circuit mpu rtc timers xin xout rxtx txrx v3p3a v3p3sys vbat vbat_rtc gnda gndd ice ir amr power fault compara to r modula to r serial ports oscilla to r/pll lcd driver dio, pulses compute engine flash memory ram 32 khz regula to r power supply 71m6543ft 71m6543ht 71m6543gt 71m6543ght temperature sensor vref batte ry rt c batte ry pwr mode control wake-up batte ry monitor spi interface host iadc0va dc9 (vb) iadc4iadc5 va dc8 (va) iadc2iadc3 neutral shunt current sensors load c b a mux and adc iadc1va dc10 (vc) iadc6iadc7 in*ic ib ia resistor dividers note: this system is referenced to neutral 3x 71m6xx3 pulse transformers neutral 71m6xx3 71m6xx3 71m6xx3 *i n = ne ut ra l curren t com0...5 seg seg/dio dio pulses, dio i 2 c or wire eeprom v3p3d lcd display downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. 71m6543ft/71m6543ht/ 71m6543gt/71m6543ght energy meter ics ? 2015 maxim integrated products, inc. 75 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com. revision history revision number revision date description pages changed 0 6/13 initial release 1 8/13 added description and speciications for 71m6543gt and 71m6543ght devices, added note in spi flash mode section about code updates, corrected part numbers listed in the reading the info page section and in the igures, updated table 12 for the external interrupts, changed the single-ended inputs from four to two, updated the description of temp_start and temp_per in table 12, updated table 12 with deinitions for stemp_t22_p, stemp_t85_p, t22_p, t85_p and umux_sel, updated chip_id description in table 12, added description for the uart section 1C69 2 10/13 removed pins 63C66 as n.c. (no connection) in the pin descriptions table 16 3 10/13 removed future product status on 71m6543ht in the ordering information table, updated the v ref error speciication in the electrical characteristics 10, 70 4 12/13 updated the cxl and cxs capacitor values from 10pf and 15pf to 22pf 12, 14 5 2/14 updated the v ref coeficients in the electrical characteristics table; removed note 2 from the ec notes; changed cxs and cxl notes in the recommended external components table; removed future status from 71m6543ght in the ordering information table 8, 10, 12, 70 6 1/15 updated the beneits and features section 1 7 12/15 added table 11; deleted table 14, and updated table numbers for new tables 11C14; updated table 12 and wording for reading the info page section, and table 20; corrected land pattern number 38, 53C62, 63, 67, 73 downloaded from: http:///

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